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Nutaq has just posted information about an intense demo where four of the company’s PicoSDR 8x8 7MHz-6GHz software-defined radio systems—based on Xilinx Virtex-6 FPGAs—are ganged to create a 32-antenna, massive-MIMO basestation that can communicate wirelessly with six UEs (user equipment systems) simultaneously. The UEs are simulated using three Xilinx ZC702 eval kits based on Zynq Z-7020 SoCs.

 

 

 

Nutaq 32-antenna massive-MIMO array.jpg

 

Nutaq’s 32-antenna massive-MIMO array

 

 

 

Here’s a Nutaq video of the demo:

 

 

 

 

 

 

All of the signal processing in this demo is performed on a laptop PC using Mathworks’ MATLAB, which generates waveforms for transmission by the simulated UEs and decodes received signals from the PicoSDR 8x8 receiver. As explained in the video, the transmission waveforms are downloaded to the BRAMs in the Zynq SoCs on the ZC706 boards, wirelessly transmitted to the massive-MIMO receiving antenna, captured by the PicoSDR 8x8 systems, and then sent back to MATLAB for decoding into separate UE constellations.

 

For more information about this demo and the PicoSDR 8x8 systems, contact Nutaq directly.

 

For more information in Xcell Daily, see “Nutaq LTE demo shows FPGA-based PicoSDR 8x8 working with Matlab LTE System Toolbox running 16-element MIMO.”

 

 

 

Shahriar Shahramian, department head for millimeter-Wave ASIC Research at Nokia Bell Labs, has a YouTube channel that he calls “The Signal Path” where he delivers high-quality introductory videos about many areas in electronics and deeply knowledgeable teardowns of equipment—often high-frequency equipment. (He’s been making these videos for nearly seven years.) His teardown videos often uncover Xilinx All Programmable devices inside the equipment he studies, and this blog is about just such an instrument: the $2595 Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator (SA and TG).

 

 

Siglent SSA3032X Spectrum Analyzer.jpg

 

 

Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator

 

 

 

A recently published teardown video by Shahramian shows you how the Siglent SSA3032X SA and TG is designed and how it works. In this 1-hour video, you get a detailed look inside of the Siglent SSA3032X SA and TG, Shahramian’s analysis of how the instrument is designed, extended demonstrations of its performance while conducting myriad RF tests, and a very good look at the components used in the instrument’s design.

 

While examining the instrument’s digital board, Shahramian points out a Xilinx Spartan-6 LX45 FPGA (at 8:40 in the video). Based on its physical location, he concludes that the FPGA is used for real-time control of the SA’s analog sections and ADC, graphics and control of its large 1024x600-pixel LCD, and monitoring of the instrument’s front-panel controls. The FPGA acts as the Spectrum Analyzer’s real-time control master, working in tandem with the on-board TI Sitara microprocessor, which is based on an ARM Cortex-A8 microprocessor.

 

 

 

Siglent SSA3032X Spectrum Analyzer Digital Board.jpg

 

 

The digital board for the Siglent SSA3032X 9kHz - 3.2GHz Spectrum Analyzer and Tracking Generator uses a Xilinx Spartan-6 FPGA for real-time instrument control and management

 

 

 

If you have the time, the video is well worth watching:

 

 

 

 

By the way, if you like Shahramian’s videos, one way you can help him is to let vendors like Siglent know you watched this video to learn about the company’s SSA3032X.

 

 

SpaceX launches 10 more Iridium NEXT comsats (and a bunch of Virtex-5QV FPGAs) into orbit

by Xilinx Employee ‎10-10-2017 02:43 PM - edited ‎10-10-2017 02:47 PM (2,277 Views)

 

On Monday, a SpaceX Falcon 9 rocket launched from Vandenberg Air Force Base in California successfully placed ten more Iridium NEXT communications satellites into low-earth orbit (LEO). This is the third such Iridium launch for SpaceX, which means that the company has placed 30 of the planned 75 Iridium NEXT comsats into LEO. (There will be 81 Iridium satellites in the completed constellation.) Each of the ten Iridium NEXT satellites in this launch incorporates several Xilinx space-grade Virtex-5QV FPGAs used to implement the satellites’ On Board Processor (OBP) hardware developed by SEAKR Engineering. (Space-grade Virtex-5QV FPGAs are the radiation-hardened version of commercial Xilinx Virtex-5 FPGAs and were developed under sponsorship by AFRL's Space Vehicles Directorate.)

 

SpaceX has posted a YouTube video of the launch that lasts 90 minutes, but assuming you don’t have time for that, here’s a 6-minute version from SciNews that starts with a 10-second countdown and ends with the successful recovery of the Falcon 9 rocket’s first stage on the landing droneship named “Just Read the Instructions”:

 

 

 

For more information on the Iridium NEXT program, see “Last week’s SpaceX launch successfully put 10 Iridium NEXT satellites (with dozens of Xilinx FPGAs) into low-earth orbit.”

 

 

 

Exactly a week ago, Xilinx introduced the Zynq UltraScale+ RFSoC family, which is a new series of Zynq UltraScale+ MPSoCs with RF ADCs and DACs and SD-FECs added. (See “Zynq UltraScale+ RFSoC: All the processing power of 64- and 32-bit ARM cores, programmable logic plus RF ADCs, DACs.”) This past Friday at the Xilinx Showcase held in Longmont, Colorado, Senior Marketing Engineer Lee Hansen demonstrated a Zynq UltraScale+ ZU28DR RFSoC with eight 12-bit, 4Gsamples/sec RF ADCs, eight 14-bit, 6.4Gsamples/sec RF DACs, and eight SD-FECs connected through an appropriate interface to National Instruments’ LabVIEW Systems Engineering Development Environment.

 

The demo system was generating signals using the RF DACs, receiving the signals using the RF ADCs, and then displaying the resulting signal spectrum using LabVIEW.

 

Here’s a 3-minute video of the demo:

 

 

 

 

 

LightReading has just posted a 5-minute video interview with Kirk Saban (Xilinx’s Senior Director for FPGA and SoC Product Management and Marketing) discussing some of the aspects of the newly announced Zynq UltraScale+ RFSoCs with on-chip RF ADCs and DACs. These devices are going to revolutionize the design of all sorts of high-end equipment that must deal with high-speed analog signals in markets as diverse as 5G communications, broadband cable, test and measurement, and aerospace/defense.

 

Here’s the video:

 

 

 

 

 

 

For more information about the new Zynq UltraScale+ RFSoC family, see “Zynq UltraScale+ RFSoC: All the processing power of 64- and 32-bit ARM cores, programmable logic plus RF ADCs, DACs.”

 

 

 

Earlier today, Xilinx formally announced delivery of the first Zynq UltraScale+ RFSoCs. (See “Zynq UltraScale+ RFSoC: All the processing power of 64- and 32-bit ARM cores, programmable logic plus RF ADCs, DACs.”) Now there’s a specification-packed video showing one of these devices in action. It’s only four minutes long, but you’ll probably need to view it at least twice to unpack everything you’ll see in terms of RF processing, ADC and DAC performance. Better strap yourself in for the ride.

 

 

 

 

For more information about the Zynq UltraScale+ RFSoC device family, please contact your friendly neighborhood Xilinx sales representative or Avnet sales representative.

 

 

You say you want a revolution

Well, you know

We all want to change the world

 

--“Revolution” written by John Lennon and Paul McCartney

 

 

Today, Xilinx announced five new Zynq UltraScale+ RFSoC devices with all of the things you expect in a Xilinx Zynq UltraScale+ SoC—a 4-core APU with 64-bit ARM Cortex A-53 processor cores, a 2-core RPU with two 32-bit ARM Cortex-R5 processors, and ultra-fast UltraScale+ programmable logic—with revolutionary new additions: 12-bit, RF-class ADCs, 14-bit, RF-class DACs, and integrated SD-FEC (Soft Decision Forward Error Correction) cores.

 

Just in case you missed the plurals in that last sentence, it’s not one but multiple RF ADCs and DACs.

 

That means you can bring RF analog signals directly into these chips, process those signals using high-speed programmable logic along with thousands of DSP48E2 slices, and then output processed RF analog signals—using the same device to do everything. In addition, if you’re decoding and/or encoding data, two of the announced Zynq UltraScale+ RFSoC family members incorporate SD-FEC IP cores that support LDPC coding/decoding and Turbo decoding for applications including 5G wireless communications, backhaul, DOCSIS, and LTE. If you’re dealing with RF signals and high-speed communications, you know just how revolutionary these parts are.

 

For everyone else not accustomed to handling RF analog signals… well you’ll just have to take my word for it. These devices are revolutionary.

 

Here’s a conceptual block diagram of a Zynq UltraScale+ RFSoC:

 

 

 

RFSoC Block Diagram.jpg 

 

 

Here’s a table that shows you some of the resources available on the new Zynq UltraScale+ RFSoC devices:

 

 

RFSoC Product Table.jpg 

 

 

As you can see from the table, you can get as many as eight 12-bit, 4Gsamples/sec ADCs or sixteen 12-bit, 2Gsamples/sec ADCs on one device. You can also get eight or sixteen 14-bit, 6.4Gsamples/sec DACs on the same device. Two of the Zynq UltraScale+ RFSoCs also incorporate eight SD-FECs. In addition, there are plenty of logic cells, DSP slices, and RAM on these devices to build just about anything you can imagine. (With my instrumentation background, I can imagine new classes of DSOs and VSTs (Vector Signal Transceivers), for example.)

 

You get numerous benefits by basing your design on a Zynq UltraScale+ RFSoC device. The first and most obvious is real estate. Putting the ADCs, DACs, processors, programmable logic, DSPs, memory, and programmable I/O on one device saves a tremendous amount of board space and means you won’t be running high-speed traces across the pcb to hook all these blocks together.

 

Next, you save the complexity of dealing with high-speed converter interfaces like JESD204B/C. The analog converters are already interfaced to the processors and logic inside of the device. Done. Debugged. Finished.

 

You also save the power associated with those high-speed interfaces. That alone can amount to several watts of power savings. These benefits are reviewed in a new White Paper titled “All Programmable RF-Sampling Solutions.

 

There’s a device family overview here.

 

And just one more thing. Today’s announcement didn’t just announce the Zynq UltraScale+ RFSoC device family. The announcement headline included one more, very important word: “Delivers.”

 

 

As in shipped.

 

 

Because Xilinx doesn’t just announce parts. We deliver them too.

 

 

For more information about the Zynq UltraScale+ RFSoC device family, please contact your friendly neighborhood Xilinx sales representative or Avnet sales representative.

 

 

 

This week, EXFO announced and demonstrated its FTBx-88400NGE Power Blazer 400G Ethernet Tester at the ECOC 2017 optical communications conference in Gothenburg, Sweden using a Xilinx VCU140 FPGA design platform as an interoperability target. The VCU140 development platform is based on a Xilinx Virtex UltraScale+ VU9P FPGA. EXFO’s FTBx-88400NGE Power Blazer offers advanced testing for the full suite of new 400G technologies including support for FlexE (Flex Ethernet), 400G Ethernet, and high-speed transceiver validation. The Flex Ethernet (FlexE) function supports one or more bonded 100GBASE-R PHYs supporting multiple Ethernet MAC operating at a rate of 10, 40, or n x 25Gbps. Flex Ethernet is a key data center technology that helps data centers deliver links that are faster than emerging 400G solutions.

 

Here’s a photo of the ECOC 2017 demo:

 

 

 

EXFO FTBx-88400NGE Power Blazer Demo.jpg 

 

 

 

This demonstration is yet one more proof point for the 400GbE standard, which will be used in a variety of high-speed communications applications including data-center interconnect, next-generation switch and router line cards, and high-end OTN transponders.

 

 

 

Last September at the GNU Radio Conference in Boulder, Colorado, Ettus Research announced the RFNoC & Vivado Challenge for SDR (software-defined radio). Ettus’ RFNoC (RF Network on Chip) is designed to allow you to efficiently harness the latest-generation FPGAs for SDR applications without being an expert firmware or FPGA developer. Today, Ettus Research and Xilinx announced the three challenge winners.

 

Ettus’ GUI-based RFNoC design tool allows you to create FPGA applications as easily as you can create GNU Radio flowgraphs. This includes the ability to seamlessly transfer data between your host PC and an FPGA. It dramatically eases the task of FPGA off-loading in SDR applications. Ettus’ RFNoC is built upon Xilinx’s Vivado HLS.

 

Here are the three winning teams and their projects:

 

 

 

 

 

Finally, here’s a 5-minute video announcing the winners along with the prizes they have won:

 

 

 

 

Feeling like it’s time to go wireless with a Zynq SoC or Zynq UltraScale+ MPSoC? The new, $59 AES-PMOD-MUR-1DX-G WiFi/Bluetooth Pmod from Avnet.com (in stock now) is a fast way to get your Zynq on the air. It’s based on the ultra-small Murata Type 1DX module and it’s compatible with any development board that has access to a dual 2x6 Pmod connection. The product includes example guidelines for Avnet’s ZedBoard and UltraZed-EG Development Kits to demonstrate use of its wireless functions from PetaLinux.

 

 

Avnet WiFi Bluetooth Pmod.jpg

 

 

Please contact Avnet directly for more information about the AES-PMOD-MUR-1DX-G WiFi/Bluetooth Pmod.

 

 

 

 

 

Novator Solutions recently licensed RFEL’s ChannelCore Flex RF channelizer IP for the heart of its NCR-2000 Channelizer server, which is built from a crate full of National Instruments (NI) PXIe modules. Using RFEL’s ChannelCore Flex RF channelizer IP, which is instantiated on NI’s PXIe-7975R FlexRIO FPGA module (based on a Xilinx Kintex-7 XC7K410T FPGA), Novator’s NCR-2000 Channelizer server can analyze thousands of RF signals with a single receiver. Ideally you’d dedicate one receiver to every signal (or RF channel) of interest. However, as the number of channels increases, that approach rapidly becomes impractical both physically and because of cost considerations. Instead, you use a channelizer.

 

 

Novator NCR-2000 Channelizer Server.jpg
 

 Novator Solutions’ NCR-2000 Channelizer server

 

 

 

If you look closely in the photo above at the NCR-2000 Channelizer server’s stable of NI PXIe modules, you’ll see an NI Vector Signal Analyzer (VSA) on the right in addition to two PXIe-7975R FlexRIO FPGA modules towards the left. VSA options include the NI PXIe-5667 3.6GHz VSA or the PXIe-5668R High Performance 26.5GHz Wideband Signal Analyzer (based on a Xilinx Kintex-7 FPGA).

 

Here’s a block diagram of Novator Solutions’ NCR-2000 Channelizer server:

 

 

 

Novator NCR-2000 Channelizer Server Block Diagram.jpg

 

Novator Solutions’ NCR-2000 Channelizer server block diagram

 

 

 

The channelizer IP running on the FPGAs at the heart of the NCR-2000 Channelizer server are based on RFEL’s ChannelCore Flex IP, which can discriminate thousands of independently defined channels across any RF bandwidth in real time. Channel parameters that can be specified to an accuracy of better than 0.06 Hz.

 

Here’s a block diagram of RFEL’s ChannelCore Flex channelizer IP:

 

 

 

RFEL ChannelCore Flex Channelizer Block Diagram.jpg

 

 

RFEL’s ChannelCore Flex channelizer IP block diagram

 

 

One key thing to note here is that this channelizer IP supports multiple inputs from multiple RF receivers. The IP block can accommodate as many as 16 inputs and dedicates separate FPGA coarse-stage resources to each input. Input parallelism can range from 1 to 16 coarse stages. With 16x input parallelism, a single ChannelCore Flex IP core can simultaneously process more than 50GHz of RF bandwidth.

 

Novator Solutions has also integrated the ChannelCore Flex IP into the heart of its new NCR-10 channelizer toolkit for NI’s USRP-2955 Software-Defined Radio Reconfigurable Device, which coincidentally is also based on a Xilinx Kintex-7 FPGA.

 

Now before you get the impression that RFEL’s ChannelCore Flex IP only runs on Xilinx Kintex-7 devices, I’d like to point out one line from the IP’s specification:

 

“Typical complex input sample rates of 500 Msps in mid-range FPGAs, with rates over 1 Gsps for certain channel plans in high-end devices.”

 

Finally, channelizers are used in a variety of applications including:

 

 

  • Software-defined/cognitive radio
  • Electronic warfare
  • Broad-spectrum surveillance
  • Communications profiling
  • Providing a direct feed to a multi-channel satellite demodulator
  • Instrumentation and measurement
  • Scientific applications

 

 

 

Please contact RFEL directly for more information about the ChannelCore Flex IP core for Xilinx All Programmable devices.

 

A 5G NR (New Radio) Progress Report from the NI 5G Innovation Lab

by Xilinx Employee ‎07-17-2017 11:25 AM - edited ‎07-17-2017 11:28 AM (10,654 Views)

 

There’s a lot of 5G research already taking place at National Instruments’ (NI’s) new 5G Innovation Lab located in Austin, Texas (announced in May) and RCR Wireless News’ Martha DeGrasse recently published a report about the lab on the publication’s Web site. In this 5G Innovation Lab, NI’s proprietary T&M equipment and software are being used by carriers, chipmakers, and equipment vendors including AT&T, Verizon, Ericsson, and Intel to develop and test 5G hardware and protocols.

 

One of the research projects DeGrasse describes involves Verizon’s 5GTF—V5GTF, the Verizon 5G Technology Forum—which is developing a 28/39GHz wireless communications platform designed to replace fiber in fixed-wireless applications. There’s a running demo of this technology in the NI 5G Research Lab that uses a 28GHz link to convey a 3Gbps digital stream between a simulated basestation and a simulated fixed-location user device. Here’s a brand new, 2-minute video of a demo:

 

 

 

 

The equipment used in this V5GTF demo includes NI’s mmWave Transceiver System which includes FPGA processing modules based on Xilinx Virtex-7 and Kintex-7 FGPAs. The FPGA processing modules handle the complex, still-in-development modulation and control protocols being developed for mmWave communications.

 

 

I’ve written about SDRs (software-defined radios) built with Analog Devices’ AD9371 dual RF transceivers and Xilinx All Programmable devices before but never on the scale of VadaTech’s AMC597 300MHz-to-6GHz Octal Versatile Wideband Transceiver, which connects four AD9371 chips over JESD204B high-speed serial interfaces with a Xilinx Kintex UltraScale KU115 FPGA (the UltraScale DSP monster with 5520 DSP48 slices) and three banks of DDR4 SDRAM (two 8Gbyte banks and one 4Gbyte bank for a total of 20Gbytes). The whole system fits into an AMC form factor. Here’s a photo:

 

 

Vadatech AMC597.jpg

 

VadaTech AMC597 300MHz-to-6GHz Octal Versatile Wideband Transceiver

 

 

 

It’s essentially a solid block of raw SDR capability jammed into a compact, 55W (typ) package. This programmable powerhouse has the RF and processing capabilities you need to develop large, advanced digital radio systems using development tools from VadaTech, Analog Devices, and Xilinx. The AMC597 is compatible with Analog Devices’ design tools for AD9371; you can develop your own FPGA-based processing configuration with Xilinx’s Vivado Design Suite and System Generator for DSP; and VadaTech supplies reference designs with VHDL source code, documentation, and configuration binary files.

 

 

 

Anthony Collins, Harpinder Matharu, and Ehab Mohsen of Xilinx have just published an application article about the 16nm Xilinx RFSoC in MicroWave Journal titled “RFSoC Integrates RF Sampling Data Converters for 5G New Radio.” Xilinx announced the RFSoC, which is based on the 16nm Xilinx Zynq UltraScale+ MPSoC, back in February (see “Xilinx announces RFSoC with 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs for 5G, other apps. When we say “All Programmable,” we mean it!”). The Xcell Daily blog with that announcement has been very popular. Last week, another blog gave more details (see “Ready for a few more details about the Xilinx All Programmable RFSoC? Here you go”), and now there’s this article in Microwave Journal.

 

This new article gets into many specifics with respect to designing the RFSoC into systems with block diagrams and performance numbers. In particular, there’s a table showing MIMO radio designs based on the RFSoC with 37% to 51% power reductions and significant pcb real-estate savings due to the RFSoC’s integrated, multi-Gbps ADCs and DACs.

 

If you’re looking to glean a few more technical details about the RFSoC, this article is the latest place to go.

 

 

 

There’s considerable 5G experimentation taking place as the radio standards have not yet gelled and researchers are looking to optimize every aspect. SDRs (software-defined radios) are excellent experimental tools for such research—NI’s (National Instruments’) SDR products especially so because, as the Wireless Communication Research Laboratory at Istanbul Technical University discovered:

 

“NI SDR products helped us achieve our project goals faster and with fewer complexities due to reusability, existing examples, and the mature community. We had access to documentation around the examples, ready-to-run conceptual examples, and courseware and lab materials around the grounding wireless communication topics through the NI ecosystem. We took advantage of the graphical nature of LabVIEW to combine existing blocks of algorithms more easily compared to text-based options.”

 

Researchers at the Wireless Communication Research Laboratory were experimenting with UFMC (universal filtered multicarrier) modulation, a leading modulation candidate technique for 5G communications. Although current communication standards frequently use OFDM (orthogonal frequency-division multiplexing), it is not considered to be a suitable modulation technique for 5G systems due to its tight synchronization requirements, inefficient spectral properties (such as high spectral side-lobe levels), and cyclic prefix (CP) overhead. UFMC has relatively relaxed synchronization requirements.

 

The research team at the Wireless Communication Research Laboratory implemented UFMC modulation using two USRP-2921 SDRs, a PXI-6683H timing module, and a PXIe-5644R VST (Vector signal Transceiver) module from National Instruments (NI)–and all programmed with NI’s LabVIEW systems engineering software. Using this equipment, they achieved better spectral results over the OFDM usage and, by exploiting UFMC’s sub-band filtering approach, they’ve proposed enhanced versions of UFMC. Details are available in the NI case study titled “Using NI Software Defined Radio Solutions as a Testbed of 5G Waveform Research.” This project was a finalist in the 2017 NI Engineering Impact Awards, RF and Mobile Communications category, held last month in Austin as part of NI Week.

 

 

5G UFMC Modulation Testbed.jpg 

 

 

5G UFMC Modulation Testbed based on Equipment from National Instruments

 

 

Note: NI’s USRP-2921 SDR is based on a Xilinx Spartan-6 FPGA; the NI PXI-6683 timing module is based on a Xilinx Virtex-5 FPGA; and the PXIe-5644R VST is based on a Xilinx Virtex-6 FPGA.

 

 

 

 

 

 

National Instruments (NI) has just announced a baseband version of its 2nd-Generation PXIe VST (Vector Signal Transceiver), the PXIe-5820, with 1GHz of complex I/Q bandwidth. It’s designed to address the most challenging RF front-end module and transceiver test applications. Of course, you program it with NI’s LabVIEW system engineering software like all NI instruments and, like its RF sibling the PXIe-5840, the PXIe-5820 baseband VST is based on a Xilinx Virtex-7 690T FPGA and a chunk of the FPGA’s programmable logic is available to users for creating real-time, application-specific signal processing using LabVIEW FPGA. According to Ruan Lourens, NI’s Chief Architect of RF R&D, “The baseband VST can be tightly synchronized with the PXIe-5840 RF VST to sub-nanosecond accuracy, to offer a complete solution for RF and baseband differential I/Q testing of wireless chipsets.”

 

 

 

NI PXIe-5820 Baseband VST.jpg 

 

NI’s new PXIe-5820 Baseband VST

 

 

 

 

How might you use this feature? Here’s a very recent, 2-minute video demonstration of a DPD (digital predistortion) measurement application that provides a pretty good example:

 

 

 

 

 

When someone asks where Xilinx All Programmable devices are used, I find it a hard question to answer because there’s such a very wide range of applications—as demonstrated by the thousands of Xcell Daily blog posts I’ve written over the past several years.

 

Now, there’s a 5-minute “Powered by Xilinx” video with clips from several companies using Xilinx devices for applications including:

 

  • Machine learning for manufacturing
  • Cloud acceleration
  • Autonomous cars, drones, and robots
  • Real-time 4K, UHD, and 8K video and image processing
  • VR and AR
  • High-speed networking by RF, LED-based free-air optics, and fiber
  • Cybersecurity for IIoT

 

That’s a huge range covered in just five minutes.

 

Here’s the video:

 

 

 

 

 

Signal Integrity Journal just published a new article titled “Addressing the 5G Challenge with Highly Integrated RFSoC,” written by four Xilinx authors. The articles discusses some potential uses for Xilinx RFSoC technology, announced in February. (See “Xilinx announces RFSoC with 4Gsamples/sec ADCs and 6.4Gsamples/sec DACs for 5G, other apps. When we say “All Programmable, we mean it!”)

 

Cutting to the chase of this 2600-word article, the Xilinx RFSoC is going to save you a ton of power and make it easier for you to achieve your performance goals for 5G and many other advanced, mixed-signal system designs.

 

If you’re involved in the design of a system like that, you really should read the article.

 

 

Adam Taylor’s MicroZed Chronicles Part 198: Building the 250Msamples/sec AD9467 FMC Card

by Xilinx Employee ‎05-30-2017 10:48 AM - edited ‎05-30-2017 10:50 AM (15,633 Views)

 

By Adam Taylor

 

 

Last week I mentioned, the Analog Devices AD9467 FMC in the blog and how we could use it with the Xilinx SDSoC development environment to capture data with a simple data-capture chain and then develop and accelerate the algorithm using a high-level language like C or C++.

 

 

Image1.jpg

 

Analog Devices AD9467 FMC and Zynq-based Avnet ZedBoard Combined

 

 

 

The AD9467 FMC contains the AD9467 ADC, which provides 16-bit quantization at sampling rates of up to 250Msamples/sec (MSPS). These specs allow us to use the AD9467 to sample Intermediate Frequency (IF) signals. An IF is used to move an RF carrier wave down from or up to a higher frequency for reception or transmission.

 

The first thing we need to do with the AD9467 board is to work out the clocking scheme we’ll use to provide the ADC with a sample clock. We have three options:

 

  1. Apply an externally generated sine-wave. This option allows us to easily change the sampling frequency. However, to ensure good convertor performance, we’ll need a low-jitter clock from a quality signal source.
  2. Use the on-board oscillator. This option provides a fixed 250MHz reference clock to the ADC. It has the advantage of being an on-board resource with a known good layout. However, its sampling frequency is fixed.
  3. Use the on-board AD9517—an SPI-controlled, 12-output clock generator. This option gives us the ability to set the sampling frequency as desired.

 

To change between the three sources, we add and remove ac coupling capacitors from the circuit to put the correct clock generator in the clock path. By default, the clock path is configured to use the external clock source.

 

However, before we can create an SDSoC Platform, we need to create a base design in Vivado. This base design interfaces with the AD9467 FMC and transfers the sampled data into the Zynq SoC’s PS (processing system) DDR memory using DMA. Rather helpfully, the AD9467 FMC comes with a Vivado example that we can use with the ZedBoard. This example design creates the structure to transfer samples into the PS DDR SDRAM using DMA.

 

To recreate this design, the first thing we need to do is download the Analog Devices Git Hub repository, which contains both the shared IP elements required and the actual Vivado design example. To ensure we are using the latest possible tool chain, select the latest tool revision from the Git Hub and download a zip of the repository or clone the repository from here.

 

To build this project, we need to be using either a Linux box or, if we are using Microsoft Windows, we’ll need to download and install CYGWIN. If you are using CYGWIN, you need to make sure you have Vivado in your path.

 

To build the project you just need to use either a terminal or CYGWIN to navigate to the AD9467_FMC directory and execute the make file for the Zed version.

 

 

Image2.jpg 

 

Make file running in CYGWIN to recreate the project

 

 

 

Once this has been recreated, we will be able to open our project in Vivado, explore the design in the block diagram, and export the design. We can then use the test application software to complete the demo.

 

 

 

Image3.jpg 

 

AD9467 FMC example design

 

 

 

As can be seen in the above example, these steps add the FMC example into the existing Zynq base hardware design so that all the other interfaces like HDMI are still available. These additional interfaces can be very useful to us. In the diagram above, you can see the highlighted path from the AD9467 receiver IP, into a DMA IP block and then an AXI Interconnect block that connects to a Zynq HP (high-performance) AXI port. This design allows the data move seamless into the PS DDR SDRAM for future processing.

 

Of course to do this we need to run some software on the Zynq SoC’s ARM Cortex-A9 processor to configure the AD9467, the AD9517, and the simple internal processing pipeline. You can download the demo application example from here on GitHub. Helpfully, it comes with batch files (one for Linux one for Windows), which are used to create the demo software application to support the Vivado design.

 

When we run this example on the Zynq SoC, we will find that it performs a number of tests prior to performing the first ADC sample capture.

 

 

 

Image4.jpg 

 

Terminal Output from ZedBoard if the FMC is present

 

 

 

The samples will be stored at 0x0800_0000 within the DDR SDRAM. Using the debug facility within SDK, we can examine these values and see that they are updated when the sampling occurs.

 

 

Image5.jpg

 

DDR Memory location at 0x0800_0000 following power cycle

 

 

 

Image6.jpg

 

DDR Memory Location at 0x0800_0000 following the samples being captured

 

 

 

With this up and working, we can now think about how we can use the base platform efficiently to implement higher-level signal-processing algorithms.

 

 

 

Code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

MicroZed Chronicles hardcopy.jpg 

  

 

  • Second Year E Book here
  • Second Year Hardback here

 

 

MicroZed Chronicles Second Year.jpg

 

 

TI’s 2-device power converter design for Remote Radio Heads looks good for any Zynq UltraScale+ MPSoC app

by Xilinx Employee ‎05-22-2017 11:11 AM - edited ‎05-23-2017 05:14 AM (15,507 Views)

 

TI has a new design example for a 2-device power converter to supply multiple voltage rails to a Xilinx Zynq UltraScale+ MPSoC for Remote Radio Heads and wireless backhaul applications, but the design looks usable across the board for many applications of the Zynq MPSoC. The two TI power-control and -conversion devices in this reference design are the TPS6508640 configurable, multi-rail PMIC for multicore processors and the TPS544C25 high-current, single-channel dc-dc converter. Here’s a simplified diagram of the design:

 

 

 

TI Remote Radio Head Power Supply Design Example.jpg

 

 

Please contact TI for more information about these power-control and –conversion devices.

 

Epiq Solutions has announced the Matchstiq S12 SDR transceiver, an expansion to the Matchstiq transceiver family, which also includes the Matchstiq S10 and S11. All three Matchstiq family members pair a Freecale i.MX6 quad-core CPU, used for housekeeping and interfacing (Ethernet, HDMI, and USB), with a Xilinx Spartan-6 LX45T FPGA installed on the company’s Sidekiq MiniPCIe card, which performs the RF signal processing for SDR. These two devices, located on separate boards, communicate over a single PCIe lane and form a reusable SDR platform for the Matchstiq transceiver family. The Matchstiq S12 employs a Dropkiq frequency-extension board to take the bottom of its tuning frequency range below 1MHz. All three Matchstiq transceiver tuners top out at 6GHz and have 50MHz of channel bandwidth. The Matchstiq S10 and S11 SDR tuners go down to 70MHz.

 

Here are the block diagrams of all three Matchstiq transceivers, which illustrate the platform nature of the basic Matchstiq design:

 

 

Epiq Solutions Matchstiq RF Transceivers.jpg

 

 

Epic Solutions Matchstiq SDR Transceiver Block Diagrams

 

 

 

And here’s a family photo:

 

 

 

Epiq Solutions Matchstiq RF Transceivers family.jpg 

 

 

Epic Solutions Matchstiq SDR Transceiver Family

 

 

 

 

 

 

 

 

“Xilinx All Programmable FPGAs and SoCs are playing a pivotal role in building 5G systems that can be easily and rapidly updated and enhanced to align with emerging standards and opportunities. The majority of the industry’s 5G proof of concepts, test beds and early commercialization trials for eMBB, URLLC, and mMTC use cases are leveraging Xilinx technology,” because “merchant silicon does not exist and ASICs are not viable this early in the 5G standardization phase. … The first wave of commercial 5G system deployments are likely to rely on these prototypes.”

 

That’s the premise of a new blog written by Xilinx’s Director Communications Strategic & Technical Marketing Harpinder Matharu and posted on the knect365.com Web site. Follow the link to read Matharu’s full blog post.

 

 

 

For more 5G coverage in Xcell Daily, see:

 

 

 

 

 

 

 

 

MathWorks Logo 2.jpg MathWorks has just scheduled five dates with worldwide venues for its new “Software-Defined Radio with Zynq using Simulink” course. The full-day, hands-on class covers design and modeling of SDR systems using MATLAB and Simulink, targeting Xilinx Zynq SoCs. Here’s an overview of the course:

 

 

  • Model and simulate RF signal chain and communications algorithms.
  • Verify the operation of baseband transceiver algorithm using real data
  • Generate HDL and C code targeting the programmable logic (PL) and processing system (PS) on the Zynq SoC to implement TX/RX.

 

 

The course costs $750 or €700, depending on the venue. The venues and dates are:

 

  • Munich, Germany – June 30 and July 27, 2017
  • Natick, Massachusetts – October 20, 2017
  • San Diego, California – November 17, 2017
  • San Jose, California – December 8, 2017

 

 

Please contact MathWorks directly for more information about this SDR course.

 

 

 

The short video below from National Instruments (NI) demonstrates the use of four of NI’s PXIe-5840 VSTs (Vector Signal Transceivers) coupled over high-speed serial links to an NI ATCA-3671 FPGA Module to analyze and process multi-GHz RF signals in real time, all controlled by NI’s LabVIEW software. The result is real-time control and display of the RF analysis. That’s a lot to pack into a 3.5-minute video.

 

 

 

 

 

 

 

NI’s 2nd-generation PXIe-5840 VST is based on a Xilinx Virtex-7 690T FPGA (see “NI launches 2nd-Gen 6.5GHz Vector Signal Transceiver with 5x the instantaneous bandwidth, FPGA programmability”) and the ATCA-3671 incorporates four more Xilinx Virtex-7 690T FPGAs, bringing a total of 14,400 DSP slices to bear on signal-processing tasks. (For information about another interesting use of NI’s ATCA-3671 FPGA Modules, see “DARPA wants you to win $2M in its Grand Spectrum Collaboration Challenge. Yes, lots of FPGAs are involved.”)

 

 

 

AT&T recently announced the development of a one-of-a-kind 5G channel sounder—internally dubbed the “Porcupine” for obvious reasons—that can characterize a 5G transmission channel using 6000 angle-of-arrival measurements in 150msec, down from 15 minutes using conventional pan/tilt units. These channel measurements capture how wireless signals are affected in a given environment. For instance, channel measurements can show how objects such as trees, buildings, cars, and even people reflect or block 5G signals. The Porcupine allows measurement of 5G mmWave frequencies via drive testing, something that was simply not possible using other mmWave channel sounders. Engineers at AT&T used the mmWave Transceiver System and LabVIEW System Design Software including LabVIEW FPGA from National Instruments (NI) to develop this system.

 

 

 

AT&T Porcupine channel sounder.jpg

 

 

AT&T “Porcupine” 5G Channel Sounder

 

 

 

NI designed the mmWave Transceiver System as a modular, reconfigurable SDR platform for 5G R&D projects. This prototyping platform offers 2GHz of real-time bandwidth for evaluating mmWave transmission systems using NI’s modular transmit and receive radio heads in conjunction with the transceiver system’s modular PXIe processing chassis.

 

The key to this system’s modularity is NI’s 18-slot PXIe-1085 chassis, which accepts a long list of NI processing modules as well as ADC, DAC, and RF transceiver modules. NI’s mmWave Transceiver System uses the NI PXIe-7902 FPGA module—based on a Xilinx Virtex-7 485T—for real-time processing.

 

 

NI PXIe-7902 FPGA Module.jpg

 

 

NI PXIe-7902 FPGA module based on a Xilinx Virtex-7 485T

 

 

NI’s mmWave Transceiver System maps different mmWave processing tasks to multiple FPGAs in a software-configurable manner using the company’s LabVIEW System Design Software. NI’s LabVIEW relies on the Xilinx Vivado Design Suite for compiling the FPGA configurations. The FPGAs distributed in the NI mmWave Transceiver System provide the flexible, high-performance, low-latency processing required to quickly build and evaluate prototype 5G radio transceiver systems in the mmWave band—like AT&T’s Porcupine.

 

 

 

What do you do if you want to build a low-cost state-of-the-art, experimental SDR (software-defined radio) that’s compatible with GNURadio—the open-source development toolkit and ecosystem of choice for serious SDR research? You might want to do what Lukas Lao Beyer did. Start with the incredibly flexible, full-duplex Analog Devices AD9364 1x1 Agile RF Transceiver IC and then give it all the processing power it might need with an Artix-7 A50T FPGA. Connect these two devices on a meticulously laid out circuit board taking all RF-design rules into account and then write the appropriate drivers to fit into the GNURadio ecosystem.

 

Sounds like a lot of work, doesn’t it? It’s taken Lukas two years and four major design revisions to get to this point.

 

Well, you can circumvent all that work and get to the SDR research by signing up for a copy of Lukas’ FreeSRP board on the Crowd Supply crowd-funding site. The cost for one FreeSRP board and the required USB 3.0 cable is $420.

 

 

FreeSRP Board.jpg

 

Lukas Lao Beyer’s FreeSRP SDR board based on a Xilinx Artix-7 A50T FPGA

 

 

 

With 32 days left in the Crowd Supply funding campaign period, the project has raised pledges of a little more than $12,000. That’s about 16% of the way towards the goal.

 

There are a lot of well-known SDR boards available, so conveniently, the FreeSRP Crowd Supply page provides a comparison chart:

 

 

FreeSRP Comparison Chart.jpg 

 

 

If you really want to build your own, the documentation page is here. But if you want to start working with SDR, sign up and take delivery of a FreeSRP board this summer.

 

 

 

Gilles Garcia, Xilinx’s Communications Business Lead, recently appeared on TelecomTV in connection with the ETSI 5G Network Infrastructure Summit, held in Sophia Antipolis just outside of Nice, France on April 6. TelecomTV’s Director of Content asked Gilles about the 5G networking challenges he’s seeing as Xilinx works with the major 5G infrastructure equipment suppliers. Gilles answered with three major groups of challenges:

 

  • Standards evolution: According to 3GPP, you should expect to continue to see changes to existing 5G standards as the industry gains experiences with 5G network build outs.

 

  • Power: It continues to be hard to achieve the required 5G network performance levels within the available power envelopes.

 

  • Ripple effect: Adoption of 5G networking standards has a ripple effect of requiring backhaul and fronthaul improvements and the introduction of all-new concepts to the mobile network such as adding machine learning to the mobile edge to automatically accommodate usage ebb and flow.

 

 

Here’s the TelecomTV video interview:

 

 

 

 

 

Here’s another amazing demo video of National Instrument’s (NI’s) PXIe-5840 VST (Vector Signal Transceiver) showing real-time, DVR-like capture of 1GHz of continuous-bandwidth RF data on a 24Tbyte RAID drive. You’d want this if you needed to capture a real-time, broad-spectrum set of RF signals for subsequent, more detailed analysis. The VST captures the broad-spectrum data and simultaneously streams it to the RAID storage box. (The NI PXIe-5840 VST is based on a Xilinx Virtex-7 690T FPGA for its real-time RF-generation and –analysis capabilities.)

 

Here’s the 2-minute video:

 

 

 

 

 

For more information about the 2nd-generation NI VST, see:

 

 

 

 

 

 

 

 

 

 

By Adam Taylor

 

I just received the most interesting email from Antti at Trenz, in which he pointed out that he had designed a 500MHz radio receiver using just four resistors, four capacitors, and a Xilinx series 7 FPGA. How did he do this? He is keeping that to himself for the moment. However, Antti thinks it would a great idea to open a challenge based upon this design to see if others in the FPGA community can explain how he achieved this. Of course, for the winners who supply the correct answer there will be Trenz goodies as prizes. (See below.)

 

The diagram below shows the components allowed to solve this challenge. You can redraw them if necessary to clarify the schematic. The values of R and C do not need to be optimized.

 

 

image1.jpg 

 

 

To prove that this is possible, the screen shots below show the input and the recovered signal inside the FPGA.

 

 

Image2.jpg

 

 

By this point I was thinking Delta Sigma ADC using the FPGA’s LVDS inputs. (There are papers and articles about this technique online.) However, Antti tells me this is not his solution and he was kind enough to provide a few hints for this challenge below:

 

 

  1. All you need to know is really in the diagram. You can print it out, take a pencil and complete the challenge. If you are not familiar with Xilinx FPGA’s you may have to read some Xilinx datasheets.
  2. You may have to read the Challenge description many times.
  3. The minimal digital circuitry used inside of the Xilinx FPGA to demonstrate the operation of this radio receiver can be made within less than two hours with Xilinx Vivado. If you are very fast, maybe in less than one.

 

 

Because they have so many Trenz prizes to give away to the winners, Antti has created three categories:

 

  • UltraFast - This is very simple. The first person who sends an email to Antti with a working solution, or with a solution that we cannot prove to be non-working, is the winner. There is no need to calculate the values for the resistors or capacitors or to make any performance estimates. Your sole goal is to be the first to solve the Challenge correctly.

 

  • Maker DIY hacker - To win in this category, you need to provide a working solution; you must implement it; and you must provide a photo of your setup and some measurement results. Bonus points are given if you use your design for some cool application.

 

  • Ultimate Theory - To win in this category, you need to provide a working solution. You will however get higher ranking if you:

 

  1. Provide some reasonable values for the resistors and capacitors or actually calculate them and provide the calculations.
  2. You provide additional solutions with fewer components (and less performance).
  3. You provide an enhanced solution adding minimal numbers of resistors and capacitors (no other components).

 

The closing date for entries is July 3rd. The judges will be Antti and myself (Adam Taylor).

 

If you want to enter your solution in any category email challenge@trenz.biz

 

 

The multi-GHz processing capabilities of Xilinx FPGAs never fails to amaze me and the following video from National Instruments (NI) demonstrating the real-time signal-generation and analysis capabilities of the NI PXIe-5840 VST (Vector Signal Transceiver) are merely one more proof point. The NI VST is designed for use in a wide range of RF test systems including 5G and IoT RF applications, ultra-wideband radar prototyping, and RFIC testing. In the demo below, this 2nd-generation NI VST is generating an RF signal spanning 1.2GHz to 2.2GHz (1GHz of analog bandwidth) containing five equally spaced LTE channels. The analyzer portion of the VST is simultaneously and in real time demodulating and decoding the signal constellations in two of the five LTE channels.

 

The resulting analysis screen generated by NI’s LabVIEW software tells the story:

 

 

NI VST Control Screen for LTE Demo.jpg 

 

The reason that the NI PXIe-5840 VST can perform all of these feats in real time is because there’s a Xilinx Virtex-7 690T FPGA inside pulling the levers, making this happen. (NI’s 1st-generation VSTs employed Xilinx Virtex-6 FPGAs.)

 

Here's the 2-minute video of the NI VST demo:

 

 

 

 

 

 

 

Please contact National Instruments directly for more information on its VST family.

 

 

For additional blogs about NI’s line of VSTs, see:

 

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.