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Jurassic Computer, Part 2: Recreating the Sinclair ZX Spectrum PC using a Spartan-6 FPGA—on Kickstarter

by Xilinx Employee ‎04-26-2017 12:33 PM - edited ‎04-26-2017 12:46 PM (1,034 Views)

 

The ZX Spectrum microcomputer developed by Sinclair Research first appeared in 1982. That’s precisely 35 years ago. According to Wikipedia, Sinclair sold more than five million ZX Spectrum computers over the decade that the “Speccy”’ was offered for sale. (“Speccy” appears to be the pet name that the ZX Spectrum’s many fans gave to this small machine, which spawned a huge ecosystem of software and hardware add-on vendors.) The Speccy was one of the UK’s first mainstream PCs and was based on a 3.5MHz Zilog Z80 microprocessor with either 16 or 48Kbytes of RAM. A 16Kbyte ROM consumed the rest of the Speccy’s 64K address space. Fast forward 35 years to 2017. There’s a new Kickstarter project to recreate the Speccy called the “ZX Spectrum Next.” 

 

Here’s a board photo of a ZX Spectrum motherboard, issue 3B, circa 1983, courtesy of Wikipedia:

 

 

Sinclair ZX Spectrum Motherboard circa 1983.jpg 

 

 

Sinclair 48K ZX Spectrum motherboard, Issue 3B. 1983, Manufactured 1984.

Photo Credit: Bill Bertram

 

 

 

The 40-pin NEC D780C chip on the right is an NEC copy of the Zilog Z80 processor and the NEC D23128C chip to the right of the processor is a 128Kbit masked ROM. The 40-pin Ferranti ULA (uncommitted logic array) on the left side of the board implements the ZX Spectrum’s video, the keyboard interface, and the analog I/O for audiotape mass storage I/O and sound. Sinclair designed many custom ULAs into its products during the 1980s—years before FPGAs became mainstream devices.

 

With 26 days left in the funding campaign, the ZX Spectrum Next project already has $402,936 in pledges which is 125% of goal. So this project is going to be funded (but there are stretch goals yet to be achieved!). The $127 pledge price for the board or $224 for the full machine look like a steal for this piece of recreated computing history.

 

There’s a nice video explaining the project on the Kickstarter page, replicated here:

 

 

 

 

Here’s what under the hood of the machine:

 

  • Processor: Z80 3.5Mhz and 7Mhz modes
  • Memory: 512Kbytes of SRAM (expandable to 1.5Mbytes internally and 2.5Mbytes externally)
  • Video: Hardware sprites, 256-color mode, Timex 8x1 mode, etc.
  • Video Output: RGB, VGA, HDMI
  • Storage: SD Card slot, with DivMMC-compatible protocol
  • Audio: 3x AY-3-8912 audio chips with stereo output + FM sound
  • Joystick: DB9 compatible with Cursor, Kempston and Interface 2 protocols (selectable)
  • PS/2 port: Mouse with Kempston mode emulation and an external keyboard
  • Special: Multiface functionality for memory access, savegames, cheats etc.
  • Tape support: Mic and Ear ports for tape loading and saving
  • Expansion: Original external bus expansion port and accelerator expansion port (for a Raspberry Pi Zero)
  • Accelerator board (optional): GPU / 1Ghz CPU / 512Mbytes of RAM
  • Network (optional): WiFi module
  • Extras: Real Time Clock (optional), internal speaker (optional)

 

 

And here’s a closeup of the ZX Spectrum’s motherboard to make the point for this blog post:

 

 

ZX Spectrum Next Motherboard with Spartan-6 LX9 Closeup.jpg

 

 

That’s right, the Spectrum ZX Next project team is using a Xilinx Spartan-6 LX9 FPGA to recreate essentially all of the above logic including the 8-bit Z80 microprocessor, three GI AY-3-8912 audio chips, the video (RGB, VGA, and HDMI), and all of the ZX Spectrum’s original and the new “Next” I/O ports. The Spartan-6 FPGA isn’t glue; it’s the entire system, except for the SRAM.

 

 

Finally, here’s an additional video demonstrating the ZX Spectrum Next PC’s capabilities and performance:

 

 

 

 

 

 

 

If you’re a Speccy fan, how can you resist?

 

 

 

Adam Taylor’s MicroZed Chronicles, Part 189: Zynq SoC XADC Sampling Modes

by Xilinx Employee ‎04-26-2017 11:04 AM - edited ‎04-26-2017 11:05 AM (723 Views)

 

By Adam Taylor

 

In some applications, we wish to maintain the phase relationship between sampled signals. The Zynq SoC’s XADC contains two ADCs, which we can operate simulateneously in lock step to maintain the phase relationship between two sampled signals. To do this, we use the sixteen auxillary inputs with Channels 0-7 assigned to ADC A and channeld 8-15 assigned to ADC B. In simultaneous mode, we can therefore perform conversions on channels 0 to 7 and at the same time, perform conversions on channels 8 to 15.

 

 

Image1.jpg 

 

 

In simultaneous mode, we can also continue to sample the on-chip parameters, however they are not sampled simultaneously. We are unable to perform automatic calibration in simultaneous mode but we can use another mode to perform calibration when needed. This should be sufficent because calibration is generally performed only on power up of the device for most applications.

 

To use the simulatenous mode, we first need a hardware design on Vivado that breaks out the AuX0 and AuX8 channels. On the Zedboard and MicroZed I/O Carrier Cards, these signals are broken out to the AMS connector. This allows me to connect signal sources to the AMS header to stimulate the I/O pin with a signal. For this example, I an using a Digilent Analog Discovery module as signal source.

  

The hardware design within the Zynq for this example appears below:

 

 

Image2.jpg

 

 

Writing the software in SDK for simultaneous mode is very similar to the other modes of operation we have used in the past. The only major difference is that we need to make sure we have configured the simultaneous channels in the sequencer. Once this is done and we have configured the input format we want—bipolar or unipolar, averaging, etc.—we can start the sequencer using the XSM_SEQ_MODE_SIMUL mode definition.

 

When I ran this on the MicroZed set up as shown above and stored 64 samples from both the AUX0 and AUX8 input using input signals that were offset by 180 degrees, I was able to recover the following waveform, which shows the phase relations ship is maintained:

 

 

Image3.jpg 

 

 

If we want, we can also use simultaneous-conversion mode with an external analog multiplexer. All we need to do is configure the design to use the external mux as we did previously. Perhaps the difference this time is that we need to use two external analog multiplexers because we need to be able to select the two channels to convert simultaneously. Also, we need only use three address bits to cover the 0-7 address range, as opposed four address bits that we needed for addressing all sixteen analog inputs when we previously used sequencer mode. We use the lower three address bits of the four available address bits.

 

 

 

Image4.jpg

 

 

 

At this point, the only XADC mode that we have not looked at is independent mode. This mode is like the XADC’s default (safe) mode, however in independent mode ADC A monitors the internal on chip parameters while ADC B samples the external inputs. Independent mode is intended to implement a monitoring mode. As such, the alarms are active so you can use this mode for implementing security and anti-tamper features in your design.

 

 

Code is available on Github as always.

 

If you want E book or hardback versions of previous MicroZed chronicle blogs, you can get them below.

 

 

 

  • First Year E Book here
  • First Year Hardback here.

 

 

MicroZed Chronicles hardcopy.jpg 

  

 

  • Second Year E Book here
  • Second Year Hardback here

 

MicroZed Chronicles Second Year.jpg 

 

 

 

Digi-Key stocking Zynq-based Red Pitaya Open Instrumentation STEMLab starter kits and accessories

by Xilinx Employee ‎04-24-2017 03:07 PM - edited ‎04-24-2017 04:22 PM (543 Views)

 

I’ve written about the Zynq-based Red Pitaya several times in Xcell Daily. (See below.) Red Pitaya is a single-board, open instrumentation platform based on the Xilinx Zynq SoC, which combines a dual-core ARM Cortex-A9 MPCore processor with a heavy-duty set of peripherals and a chunk of Xilinx 7 series programmable logic. Red Pitaya packages its programmable instrumentation board with probes, power supply, and an enclosure and calls it the STEMlab. I’ve just discovered the STEMlab page on the Digi-Key site with inventory levels, so if you want to get into programmable instrumentation in a hurry, this is a good place to start.

 

The page lists three STEMlab starter kits:

 

 

 

27901 Red Pitaya Stemlab with accessories.jpg 

 

 

Red Pitaya 27901 STEMlab kit with scope and logic probes

 

 

 

For more articles about the Zynq-based Red Pitaya, see:

 

 

 

 

 

 

intoPIX announces IP core support for 8K TICO video compression with <1msec end-to-end latency

by Xilinx Employee ‎04-21-2017 02:01 PM - edited ‎04-21-2017 02:16 PM (523 Views)

 

Today, intoPIX announced that it’s lightweight TICO video-compression IP cores for Xilinx FPGAs can now support frame resolutions and rates to 8K60p as well as the previously supported HD and 4K resolutions. Currently, the compression cores support 10-bit, 4:2:2 workflows but intoPIX also disclosed in a published table (see below) that a future release of the IP core will support 4:4:4 color sampling. The TICO compression standard simplifies the management of live and broadcast video streams over existing video network infrastructures based on SDI and Ethernet by reducing the bandwidth requirements of high-definition and ultra-high-definition video at compression ratios as large as 5:1 (visually lossless at ratios to 4:1). TICO compression supports live video streams through its low latency—less than 1msec end-to-end.

 

Conveniently, intoPIX has published a comprehensive chart showing its various TICO compression IP cores and the Xilinx FPGAs that can support them. Here’s the intoPIX chart:

 

 

intoPIX TICO Compression Table for Xilinx FPGAs.jpg 

 

 

Note that the most cost-effective Xilinx FPGAs including the Spartan-6 and Artix-7 families support TICO compression at HD and even some UHD/4K video formats while the Kintex-7, Virtex-7, and UltraScale device families support all video formats through 8K.

 

Please contact intoPIX for more information about these IP cores.

 

 

Avnet’s MiniZed based on single-core Xilinx Zynq Z-7007S is “coming soon” to a Web page near you

by Xilinx Employee ‎04-20-2017 11:14 AM - edited ‎04-25-2017 04:20 PM (1,041 Views)

 

I got a heads up on a new, low-end dev board called the “MiniZed” coming soon from Avnet and found out there’s a pre-announcement Web page for the board. Avnet’s MiniZed is based on one of the new Zynq Z-7000S family members with one ARM Cortex-A9 processor. It will include both WiFi and Bluetooth RF transceivers and, according to the MiniZed Web page, will cost less than $100!

 

Here’s the link to the MiniZed Web page and here’s a slightly fuzzy MiniZed board photo:

 

 

Avnet MiniZed 2.jpg
 

 

Avnet MiniZed (coming soon, for less than $100)

 

 

If I’m not mistaken, that’s an Arduino header footprint and two Digilent Pmod headers on the board, which means that a lot of pretty cool shields and Pmods are already available for this board (minus the software drivers, at least for the Arduino shields).

 

 

I know you’ll want more information about the MiniZed board but I simply don’t have it. So please contact Avnet for more information or register for the info on the MiniZed Web page.

 

The Vivado Design Suite HLx Editions 2017.1 release is now available for download. The Vivado HL Design Edition and HL System Edition now support partial reconfiguration. Partial reconfiguration is available for the Vivado WebPACK Edition at a reduced price.

 

Xilinx partial reconfiguration technology allows you to swap FPGA-based functions in and out of your design on the fly, eliminating the need to fully reconfigure the FPGA and re-establish links. Partial reconfigurability gives you the ability to update feature sets in deployed systems, fix bugs, and migrate to new standards while critical functions remain active. This capability dramatically expands the flexible use of Xilinx All Programmable designs in a truly wide variety of applications.

 

For example, a detailed article published on the WeChat Web site by Siglent about the company’s new, entry-level SDS1000X-E DSO family—based on a Xilinx Zynq Z-7020 SoC—suggests that the new DSO family’s system design employs the Zynq SoC’s partial-reconfiguration capability to further reduce the parts count and the board footprint: “The PL section has 220 DSP slices and 4.9 Mb Block RAM; coupled with high throughput between the PS and PL data interfaces, we have the flexibility to configure different hardware resources for different digital signal processing.” (See “Siglent 200MHz, 1Gsample/sec SDS1000X-E Entry-Level DSO family with 14M sample points is based on Zynq SoC.”)

 

 

 

Siglent SDS1202X-E DSO.jpg
 

 

 

Siglent’s new, entry-level SDS1000X-E DSO family is based on a Xilinx Zynq Z-7020 SoC

 

 

 

In addition, the Vivado 2017.1 release includes support for the Xilinx Spartan-7 7S50 FPGA (Vivado WebPACK support will be in a later release). The Spartan-7 FPGAs are the lowest-cost devices in the 28nm Xilinx 7 series and they’re optimized for low, low cost per I/O while delivering terrific performance/watt. Compared to Xilinx Spartan-6 FPGAs, Spartan-7 FPGAs run at half the power consumption (for comparable designs) and with 30% more operating frequency. The Spartan-7 S50 FPGA is a mid-sized family member with 52,160 logic cells, 2.7Mbits of BRAM, 120 DSP slices, and 250 single-ended I/O pins. It’s a very capable FPGA. (For more information about the Spartan-7 FPGA family, see “Today, there are six new FPGAs in the Spartan-7 device family. Want to meet them?” and “Hot (and Cold) Stuff: New Spartan-7 1Q Commercial-Grade FPGAs go from -40 to +125°C!”)

 

 

Spartan-7 Family Table with 1Q devices.jpg 

 

Spartan-7 FPGA Family Table

 

 

 

 

 

Mega65 Logo.jpgThe MEGA65 is an open-source microcomputer modeled on the incredibly successful Commodore 64/65 circa 1982-1990. Ye olde Commodore 64 (C64)—introduced in 1982—was based on an 8-bit MOS Technology 6510 microprocessor, which was derived from the very popular 6502 processor that powered the Apple II, Atari 400/800, and many other 8-bit machines in the 1980s. The 6510 processor added an 8-bit parallel I/O port to the 6502, which no doubt dropped the microcomputer’s BOM cost a buck or two. According to Wikipedia, “The 6510 was only widely used in the Commodore 64 home computer and its variants.” Also according to Wikipedia, “For a substantial period (1983–1986), the C64 had between 30% and 40% share of the US market and two million units sold per year, outselling the IBM PC compatibles, Apple Inc. computers, and the Atari 8-bit family of computers.”

 

Now that is indeed a worthy computer to serve as a “Jurassic Park” candidate and therefore, the non-profit MEGA (Museum of Electronic Games & Art), “dedicated to the preservation of our digital heritage,” is supervising the physical recreation of the Commodore 64 microcomputer (mega65.org). It’s called the MEGA65 and it’s software-compatible with the original Commodore 64, only faster. (The 6510 processor emulation in the MEGA65 runs at 48MHz compared to the original MOS Technology 6510’s ~1MHz clock rate.) MEGA65 hardware designs and software are open-source (LGPL).

 

How do you go about recreating the hardware of a machine that’s been gone for 25 years? Fortunately, it’s a lot easier than extracting DNA from the stomach contents of ancient mosquitos trapped in amber. Considering that this blog is appearing in Xcell Daily on the Xilinx Web site, the answer’s pretty obvious: you use an FPGA. And that’s exactly what’s happening.

 

A few days ago, the MEGA65 team celebrated initial bringup of the MEGA65 pcb. You can read about the bringup efforts here and here is a photo of the pcb:

 

 

MEGA65 pcb.jpg 

 

The first MEGA65 PCB

 

 

 

The MEGA65 pcb is designed to fit into the existing Commodore 65 plastic case. (The Commodore 65 was prototyped but not put into production.)

 

Sort of gives a new meaning to “single-chip microcomputer,” does it not. That big chip in the middle of the board is an Xilinx Artix-7 A200T. It implements the Commodore 64’s entire motherboard in one programmable logic device. Yes, that includes the RAM. The Artix-7 A200T FPGA has 13.14Mbits of on-chip block RAM. That’s more than 1.5Mbytes of RAM, or 25x more RAM than the original Commodore 64 motherboard, which used eight 4164 64Kbit, 150nsec DRAMs for RAM storage. The video’s a bit improved too, from 160x200 pixels, with a maximum of four colors per 4x8 character block, or 320x200 pixels, with a maximum of two colors per 8x8 character block, to a more modern 1920x1200 pixels with 12-bit color (23-bit color is planned). Funny what 35 years of semiconductor evolution can produce.

 

What’s the project’s progress status? Here’s a snapshot from the MEGA65 site:

 

 

 

MEGA65 Progress.jpg

 

 

MEGA65 Project Status

 

 

 

And here’s a video of the MEGA65 in action:


 

 

 

 

 

Remember, what you see and hear is running on a Xilinx Artix-7 A200T, configured to emulate an entire Commodore 64 microcomputer. Most of the code in this video was written in the Jurassic period of microcomputer development. If you’re of a certain age, these old programs should bring a chuckle or perhaps just a smile to your lips.

 

 

Note: You’ll find a MEGA65 project log by Antti Lukats here.

 

 

 

 

 

 

What do you do if you want to build a low-cost state-of-the-art, experimental SDR (software-defined radio) that’s compatible with GNURadio—the open-source development toolkit and ecosystem of choice for serious SDR research? You might want to do what Lukas Lao Beyer did. Start with the incredibly flexible, full-duplex Analog Devices AD9364 1x1 Agile RF Transceiver IC and then give it all the processing power it might need with an Artix-7 A50T FPGA. Connect these two devices on a meticulously laid out circuit board taking all RF-design rules into account and then write the appropriate drivers to fit into the GNURadio ecosystem.

 

Sounds like a lot of work, doesn’t it? It’s taken Lukas two years and four major design revisions to get to this point.

 

Well, you can circumvent all that work and get to the SDR research by signing up for a copy of Lukas’ FreeSRP board on the Crowd Supply crowd-funding site. The cost for one FreeSRP board and the required USB 3.0 cable is $420.

 

 

FreeSRP Board.jpg

 

Lukas Lao Beyer’s FreeSRP SDR board based on a Xilinx Artix-7 A50T FPGA

 

 

 

With 32 days left in the Crowd Supply funding campaign period, the project has raised pledges of a little more than $12,000. That’s about 16% of the way towards the goal.

 

There are a lot of well-known SDR boards available, so conveniently, the FreeSRP Crowd Supply page provides a comparison chart:

 

 

FreeSRP Comparison Chart.jpg 

 

 

If you really want to build your own, the documentation page is here. But if you want to start working with SDR, sign up and take delivery of a FreeSRP board this summer.

 

 

 

I don’t get to do too much hands-on work while writing Xcell Daily but today was an exception. Today, I took delivery of the new Digilent Discovery Portable Logic Analyzer and Digital Pattern Generator. This diminutive USB instrument measures about 3.25 inches on a side and costs a mere $199.99. For that, you get a 24-channel USB logic analyzer capable of 200Msamples/sec with simple single-ended leads and 800Msamples/sec on fewer channels with Digilent’s High Speed Adapter. (See “$199.99 Digital Discovery from Digilent implements 800Msample/sec logic analyzer, pattern generator. Powered by Spartan-6” for more information.)

 

 

 

Digilent Digital Discovery.jpg

 

 

Digilent Digital Discovery Logic Analyzer Kit

 

 

 

For comparison, my first logic analyzer was an engineering prototype of the HP 1615A, HP’s first timing/state analyzer. I borrowed this prototype instrument from HP’s Colorado Springs Division back in late 1977 to help debug a nagging problem with the I/O backplane of the HP 9845A Desktop Computer. The HP 1615A offered a “blazing” timing capture rate of 20Msamples/sec for 24 channels. Most important for me, it had a 5nsec “glitch capture” feature, which allowed me to see the I/O glitches taking place on the I/O backplane at the maxed-out DMA transfer rate of 400Ktransfers/sec. The HP 1615A logic analyzer cost $6800 back in the day and it sold like hotcakes. (For an affectionate history of HP’s entry into the logic analyzer business, see “Logic State Analyzer Birthing Pains” by Chuck House on the HP Memory Project Web site, hpmemoryproject.org.)

 

 

 

HP 1615 Logic Analyzer.jpg

 

 

The HP 1615A Logic Analyzer circa 1978 (Photo courtesy Hewlett-Packard Company)

 

 

 

Well, it’s exactly 40 years later and see what time, Digilent, and Xilinx FPGA technology have wrought. Digilent’s $199.99 Digital Discovery provides the same number of logic-analysis channels as the $6800 HP 1615A but runs 10x to 40x faster and has a 2Gbit acquisition buffer. (The HP 1615A had a 6Kbit acquisition buffer, but that was 40 years ago.) In addition, the Digilent Digital Discovery can not only display digital signals, it can decode and trigger on commonly used serial-bus protocols including SPI, I²C, UART, I2S, and CAN. Of course, none of those even existed 40 years ago except for the UART NRZ protocol.

 

So, is the Digilent Digital Discovery easy to use? The user interface for this instrument is Digilent’s GUI-based Waveforms 2015 application, which you download from the Web and install. I downloaded the Waveforms 2015 installer and immediately ran into a problem. My Xilinx-provided laptop lacked Microsoft’s Visual C++ 2013 and Visual C++ Redistributable Package. Waveforms 2015 generously offered to install the missing Microsoft package for me. I clicked “yes,” and Waveforms then tried to install the Microsoft C runtime package—and failed. Without too much trouble, I found the software on the Microsoft Web site, downloaded it, and installed it manually. Then I restarted the Waveforms 2015 installation and completed that successfully.

 

When I ran Waveforms 2015, it went looking for the Digilent Digital Discovery module, which I intentionally had not yet plugged into my laptop’s USB port. After getting the expected complaint from Waveforms 2015, I plugged the Digital Discovery into a USB port and everything started working just fine.

 

I’d known for a couple of weeks that Digilent was sending this instrument to me, so I had decided beforehand how I wanted to generate my initial test waveforms. It seemed to me that the fastest and simplest test-signal generator I could use that would be interesting was a low-cost Sparkfun RedBoard Arduino clone and an Adafruit Motor Control Shield v2, which Radio Shack had just put on sale as part of its “inventory reduction” program. (Fortunately, the Digital discovery is 5V-tolerant (I checked), because the RedBoard is a 5V board.)

 

When running the supplied “MotorParty” Arduino Sketch, the Sparkfun RedBoard continuously writes I2C commands to an H-bridge driver IC on the Adafruit Motor Control Shield to spin up a dc motor. It then then spins the motor down, reverses direction, rinses, and repeats. The MotorParty Sketch also generates a variable, TTL-level PWM signal to drive a hobby servo. I used the Digital Discovery to capture both waveforms.

 

By the way, I did all of this without taking a peek at the manual.

 

First, I hooked up the Digital Discovery to the Adafruit Motor Control Shield’s I2C pins (driven by the Sparkfun RedBoard) and set up the Logic Analyzer for I2C. It’s pretty easy. You just select I2C and the I2C clock and data lines show up on the first two channels of the logic analyzer. After initially messing up these two connections (hey, I’ve got a 50% chance of getting it right, plus I did get ground connected correctly), I was rewarded with this waveform display with the I2C traffic automatically decoded:

 

 

 

I2C Waveform Capture from Adafruit Motor Shield dc motor control.jpg

 

 

Digilent Digital Discovery I2C Waveform Display

 

 

 

OK, let’s see how well I do when I only need to connect one signal: the PWM signal driving the servo. Hobby servos use a very simple 1-wire PWM interface where the width of the logic pulse positions the servo. This protocol was created back in the pre-microprocessor days when we used RC oscillators to drive servos.

 

Here’s a 30-second video showing you how easy it is to look at continuously changing digital waveforms using the Digilent Digital Discovery (once you set the trigger correctly).

 

 

 

 

 

Again, setting up the Digital Discovery to capture this waveform is pretty simple, pretty intuitive.

 

As a reminder, these logic-analysis features are all implemented inside of one Xilinx Spartan-6 LX25 FPGA coupled to one DDR3 SDRAM serving as a really large capture buffer. I’ve yet to experiment with the other Digital discovery features including the digital pattern generator and digital I/O, but this is an amazingly powerful “bit of kit” with a nice GUI-based interface for $199.99.

 

 

Digilent Digital Discovery Module Board.jpg

 

Digilent’s Digital Discovery is based on a Xilinx Spartan-6 FPGA

 

 

 

Note: For more information about the Digital Discovery, contact Digilent directly.

 

 

 

 

Hours after I posted yesterday’s blog about Siglent’s new sub-$400, Zynq-powered SDS1000-E family of 2-channel, 200MHz, 1Gsamples/sec DSOs (see “Siglent 200MHz, 1Gsample/sec SDS1000X-E Entry-Level DSO family with 14M sample points is based on Zynq SoC”), EEVblog’s Dave Jones posted a detailed, 25-minute teardown video of the very same scope, which clearly illustrates just how Siglent reached this incredibly low price point.

 

One way Siglent achieved this design milestone was to use one single board to implement all of the scope’s analog and digital circuitry. However, 8- or 10-layer pcbs are expensive, so Siglent needed to minimize that single board’s size and one way to do that is to really chop the component count on the board. To do that without cutting functions, you need to use the most highly integrated devices you can find, which is probably why Siglent’s design engineers selected the Xilinx Zynq Z-7020 SoC as the keystone for this DSO’s digital section. As discussed yesterday, the use of the Zynq Z-7020 SoC allowed Siglent’s design team to introduce advanced features from the company’s high-end DSOs and put them into these entry-level DSOs with essentially no increase in BOM cost.

 

Here’s a screen capture from Dave’s new teardown video showing you what the new Siglent DSO’s main board looks like. That’s Dave’s finger poised over the Xilinx Zynq SoC (under the heat sink), which is flanked to the left and right by the two Samsung K4B1G1646I 1Gbit (64Mx16) DDR3 SDRAM chips used for waveform capture and the display buffer—among other things.

 

 

Siglent SDS1202X-E Motherboard.jpg 

 

 

As discussed yesterday, the Zynq SoC’s two on-chip ARM Cortex-A9 processors can easily handle the scope’s GUI and housekeeping chores. Its on-chip programmable logic implements the capture buffer, the complex digital triggering, and the high-speed computation needed for advanced waveform math and the 1M-point FFT. Finally, the Zynq SoC’s programmable I/O and SerDes transceiver pins make it easy to interface to the scope’s high-speed ADC and the DDR3 memory needed for the deep, 14M-point capture buffer and the display memory for the DSO’s beautiful color LCD with 256 intensity levels. (All this is discussed in yesterday’s Xcell Daily blog post about these new DSOs.)

 

Here’s a photo of that Siglent screen from one of Dave’s previous videos, where he uses a prototype of this Siglent DSO to troubleshoot and fix a malfunctioning HP 54616B DSO that had been dropped:

 

 

Siglent SDS1202X-E DSO Screen Shot.jpg 

 

 

 

Note: Since sending this prototype to Dave, Siglent has apparently decided to bump the bandwidth of these DSOs to 200MHz. Just another reminder of how competitive this entry-level DSO market has become, and how the Zynq SoC's competitive advantages can be leveraged in a system-level design.

 

 

Here’s Dave’s teardown video:

 

 

 

 

 

Siglent’s new SDS1000X-E family of entry-level DSOs (digital sampling oscilloscopes) feature 200MHz of bandwidth with a 1G sample/sec sample rate in the fastest family members, 14M sample points in all family models, 256 intensity levels, and a high-speed display update rate of 400,000 frames/sec. The new DSOs also include many advanced features not often found on entry-level DSOs including intelligent triggering, serial bus decoding and triggering, historical mode and sequence mode, a rich set of measurement and mathematical operations, and a 1M-point FFT. The SDS1000X-E DSO family is based on a Xilinx Zynq Z-7020 SoC, which has made it cost-effective for Siglent to migrate its high-end SPO (Super Fluorescent Oscilloscope) technology to this new entry-level DSO family.

 

 

 

Siglent SDS1202X-E DSO.jpg 

 

 

Siglent’s new, entry-level SDS1000X-E DSO family is based on a Xilinx Zynq Z-7020 SoC

 

 

 

According to this WeChat article published in January by Siglent (Ding Yang Technology in China), the Zynq SoC “is very suitable for data acquisition, storage and digital signal processing in digital oscilloscopes.” In addition, the high-speed, high-density, on-chip interconnections between the Zynq SoC’s PS (processor system) and PL (programmable logic) “effectively solve” the traditional digital storage oscilloscope CPU and FPGA data-transmission bottlenecks, which reduces the DSO’s dead time between triggers and increases the waveform capture and display rates. According to the article, the system design employs four AXI ports operating between the Zynq PS and PL to achieve 8Gbytes/sec data transfers—“far greater than the local bus transmission rate” achievable using chip-to-chip I/O, with far lower power consumption.

 

The Zynq SoC’s combination of ARM Cortex-A9 software-driven processing and on-chip programmable logic also reduces hardware footprint and facilitates integration of high-performance processing systems into Siglent’s compact, entry-level oscilloscopes. The article also suggests that the DSO system design employs the Zynq SoC’s partial-reconfiguration capability to further reduce the parts count and the board footprint: “The PL section has 220 DSP slices and 4.9 Mb Block RAM; coupled with high throughput between the PS and PL data interfaces, we have the flexibility to configure different hardware resources for different digital signal processing.”

 

Further, the SDS1000X-E DSO family’s high-speed ADC uses high-speed differential-pair signaling to connect directly to the Zynq SoC’s high-speed SerDes transceivers, which guarantee’s “stable and reliable access” to the ADCs’ 1Gbyte/sec data stream while the Zynq SoC’s on-chip DDR3 controller operating at 1066Mtransfers/sec allows “the use of single-chip DDR3 to meet the real-time storage of the ADC output data requirements.”

 

Siglent has also used the Zynq SoC’s PL to implement the DSOs’ high-sensitivity, low-jitter, zero-temperature-drift digital triggering system, which includes many kinds of intelligent trigger functions such as slope, pulse width, video, timeout, rungs, and patterns that can help DSO users more accurately isolate waveforms of interest. Advanced bus-protocol triggers and bus events (such as the onset of I2C bus traffic or UART-specific data can also serve as trigger conditions, thanks to the high-speed triggering ability designed into the Zynq SoC’s PL. These intelligent triggers greatly facilitate debugging and add considerable value to the new Siglent entry-level DSOs.

 

Here’s a translated block diagram of the SDS1000X-E DSO family’s system design:

 

 

 

Siglent SDS1202X-E DSO Block Diagram 4.jpg 

 

 

The new SDS1000X-E DSO family illustrates the result of selecting a Zynq SoC as the foundation for a system design. The large number of on-chip resources permit you to think outside of the box when it comes to adding features. Once you’ve selected a Zynq SoC, you no longer need to think about cramming code into the device to add features. With the Zynq SoC’s hardware, software, and I/O programmability, you can instead start thinking up new features that significantly improve the product’s competitive position in your market.

 

This is precisely what Siglent’s engineers were able to do. Once the Zynq SoC was included in the design, the designers of this entry-level DSO family were able to think about which high-performance features they wished to migrate to their new design.

 

 

Short, 2-minute video gives first public view of low-cost Spartan-7 FPGA in action, operating on a board

by Xilinx Employee ‎03-31-2017 03:14 PM - edited ‎03-31-2017 03:14 PM (3,128 Views)

 

This short, 2-minute video shows a live Spartan-7 7S50 FPGA operating on a board, running a MicroBlaze soft processor connected to DDR3 SDRAM as a demo. The 28nm Spartan-7 device family comes in small form-factor packages—as small as 8x8mm. You design systems based on Spartan-7 devices with the Xilinx Vivado HL Design Suite tools.

 

 

 

 

These devices are available for ordering now and operators are standing by.

 

 

 

InnoRoute has just started shipping its TrustNode extensible, ultra-low-latency (2.5μsec) IPv6 OpenFlow SDN router as a pcb-level product. The design combines a 1.9GHz, quad-core Intel Atom processor running Linux with a Xilinx FPGA to implement the actual ultra-low-latency router hardware. (You’re not implementing that as a Linux app running on an Atom processor!) The TrustNode Router reference design features twelve GbE ports. Here’s a photo of the TrustNode SDN Router board:

 

 

InnoRoute TrustNode SDN Router Board.jpg 

 

InnoRoute TrustNode SDN Router Board with 12 GbE ports

 

 

Based on the pcb layout in the photo, it appears to me that the Xilinx FPGA implementing the 12-port SDN router is under that little black heatsink in the center of the board nearest to all of the Ethernet ports while the quad-core processor running Linux must be sitting there in the back under that great big silver heatsink with an auxiliary cooling fan, near the processor-associated USB ports and SDcard carrier.

 

InnoRoute’s TrustNode Web page is slightly oblique as to which Xilinx FPGA is used in this design but the description sort of winnows the field. First, the description says that you can customize InnoRoute’s TrustNode router design using the Xilinx Vivado HL Design Suite WebPACK Edition—which you can download at no cost—so we know that the FPGA must be a 28nm series 7 device or newer. Next, the description says that the design uses 134.6k LUTs, 269.2k flip-flops, and 12.8Mbits of BRAM. Finally, we see that the FPGA must be able to handle twelve Gigabit Ethernet ports.

 

The Xilinx FPGA that best fits this description is an Artix-7 A200.

 

You can use this TrustNode board to jump into the white-box SDN router business immediately, or at least as fast as you can mill and drill an enclosure and screen your name on the front. In fact, InnoRoute has kindly created a nice-looking rendering of a suggested enclosure design for you:

 

 

InnoRoute TrustNode Router Enclosure.jpg

 

 

InnoRoute TrustNode SDN Router (rendering)

 

 

The router’s implementation as IP in an FPGA along with the InnoRoute documentation and the Vivado tools mean that you can enhance the router’s designs and add your special sauce to break out of the white box. (White Box Plus? White Box Permium? White Box Platinum? Hey, I’m from marketing and I’m here to help.)

 

This design enhancement and differentiation are what Xilinx All Programmable devices are especially good at delivering. You are not stuck with some ASSP designer’s concept of what your customers need. You can decide. You can differentiate. And you will find that many customers are willing to pay for that differentiation.

 

 

Note: Please contact InnoRoute directly for more information on the TrustNode SDN Router.

One more low-cost Zynq SoC dev board, from a reader/spelunker designing SDR cave radios

by Xilinx Employee ‎03-29-2017 12:30 PM - edited ‎03-29-2017 02:45 PM (1,078 Views)

 

A blog post from earlier this week, “Seven low-cost Zynq dev and training boards: a quick review,” prompted an email from Graham Naylor in the UK. Naylor informed me that I’d not mentioned his favorite Zynq-based board, the Trenz TE0722, in that blog post—and then he told me how he’s using the Trenz board (which is really more of a low-cost SOM rather than a training/dev board). During the day, Naylor measures neutron pulses from an ionization chamber using the Zynq-based Red Pitaya open instrumentation platform. (I’ve written many blogs about the Red Pitaya, listed below.) For fun, it appears that Naylor and colleague Pete Allwright design cave radios. If you’ve never heard of a cave radio, you’re in good company because I hadn’t either.

 

Naylor sent me a preprint of an article that will appear in the quarterly BCRA’s Cave Radio & Electronics Group Journal, in the June 2017 issue. (The BCRA is the British Cave Research Association.) Naylor’s and Allwright’s article, titled “Outlining the Architecture of the Nicola 3Z Cave Radio,” discusses the design of a new version of the Nicola 3 rescue radio designed to be used by cave rescue teams for underground communications.

 

The original Nicola 3 radio was based on a Xilinx Spartan-3E FPGA supplied on a module from OHO Elektronik. The FPGA implemented an SDR design for a radio that performs SSB modulation and demodulation using an 87KHz carrier wave. Radio transmission does not occur through the air but through the ground using a couple of electrodes jammed into the earthen floor of the cave. (We’re in a cave, remember?) A little water poured on the earth interface helps improve transmission/reception.

 

 

Nicola 3 Cave Radio in Use.jpg

 

 

Nicola 3 radio on test in Reservoir Hole, Mendip, UK (Photo: Mendip Cave Rescue)

 

 

Xilinx introduced the 90nm Spartan-3E in 2005, so the Nicola cave radio development team has upgraded the Nicola design to the Zynq Z-7010 SoC, which resides on a low-cost Trenz TE0722 SOM. Trenz sells one of these boards for just €64.00 and if you want 500 pieces, the price drops to €48.00.

 

 

 

Trenz TE0722 Zynq SOM.jpg

 

Trenz TE0722 Zynq SOM

 

 

The new radio is called the Nicola 3Z. (I'm guessing "Z" is for "Zynq.") The FPGA fabric in the Zynq SoC implements the SDR functions in the Nicola 3Z radio including the SSB class D modulator, which drives an H-bridge driver for transmission; the receiver’s SSB filter, decimator, and demodulator; and an AGC block implemented on a soft-core Xilinx PicoBlaze 8-bit microcontroller, which is also instantiated in the Zynq SoC’s FPGA. There’s a second PicoBlaze instantiation on chip for housekeeping. That Zynq Z-7010 SoC may be a low-end part, but it’s plenty busy in the Nicola 3Z radio’s design.

 

 

 

Note: For more information about the Zynq-based Red Pitaya open instrumentation platform, see:

 

 

 

Seven low-cost Zynq dev and training boards: a quick review

by Xilinx Employee on ‎03-27-2017 01:40 PM (3,389 Views)

 

With last week’s introduction of the Digilent Arty Z7 Zynq SoC training and dev board, I felt it was time to review some of the low-cost boards that occupy an outsized piece of mindshare in my head. So here are seven that have appeared previously in the Xcell Daily blog, listed in alphabetical order by vendor:

 

 

 

 

Analog Devices ADALM-PLUTO ($149): Students from all levels and backgrounds looking to improve their RF knowledge will want to take a look at the new ADALM-PLUTO SDR USB Learning Module from Analog Devices. The $149 USB module has an RF range of 325MHz to 3.8GHz with separate transmit and receive channels and 20MHz of instantaneous bandwidth. It pairs two devices that seem made for each other: an Analog Devices AD9363 Agile RF Transceiver and a Xilinx Zynq Z-7010 SoC.

 

 

Analog Devices ADALM-PLUTO SDR USB Learning Module.jpg 

 

Analog Devices’ $149 ADALM-PLUTO SDR USB Learning Module

 

 

 

 

 

 

Digilent ARTY Z7 ($149 to $209): The first thing you’ll note from the Arty Z7 dev board photo is that there’s a Zynq SoC in the middle of the board. You’ll also see the board’s USB, Ethernet, Pmod, and HDMI ports. On the left, you can see double rows of tenth-inch headers in an Arduino/chipKIT shield configuration. There are a lot of ways to connect to this board, which should make it a student’s or experimenter’s dream board considering what you can do with a Zynq SoC.

 

 

Digilent Arty Z7.jpg 

 

Digilent Arty Z7 dev board for makers and hobbyists

 

 

 

Digilent PYNQ-Z1 ($229): PYNQ is an open-source project that makes it easy for you to design embedded systems using the Xilinx Zynq-7000 SoC using the Python language, associated libraries, and the Jupyter Notebook, which is a pretty nice, collaborative learning and development environment for many programming languages including Python. PYNQ allows you to exploit the benefits of programmable logic used together with microprocessors to build more capable embedded systems with superior performance when performing embedded tasks.

 

 

PYNQ-Z1.jpg

 

Digilent PYNQ-Z1 Dev Board

 

 

 

Krtkl’s snickerdoodle ($95 to $195): The amazing, Zynq-based “snickerdoodle one” is a low-cost, single-board computer with wireless capability based on the Xilinx Zynq Z-7010 SoC, available for purchase on the Crowd Supply crowdsourcing Web site.

 

 

Snickerdoodle.jpg

 

Krtkl’s Zynq-based, WiFi-enabled Snickerdoodle Dev Board

 

 

 

National Instruments myRIO ($400 to $1001): The NI myRIO hardware/software development platform for NI’s LabVIEW system design software is based on the Zynq-7010 All Programmable SoC. About the size of a small paperback book (so that it easily drops into a backpack), the NI myRIO sports ten analog inputs, six analog outputs, left and right audio channels, 40 digital I/O lines (SPI, I2C, UARD, PWM, rotary encoder) and an on-board, 3-axis accelerometer, and two 34-pin expansion headers.

 

 

NI myRIO Board Photo.jpg

 

The Zynq-based NI myRIO

 

 

 

National Instruments RoboRIO ($435 for FRC teams): The NI roboRIO robotic controller was specifically designed for the FIRST Robotics Competition (FRC). The FRC event is a particular passion for NI’s founder, Dr. James Truchard.

 

 

 

NI roboRIO.jpg

 

NI roboRIO for First Robotics Competition teams

 

 

 

 

Trenz ZynqBerry (€79.00 to €109.00): The Trenz Electronic TE0726 ZynqBerry Dev Board puts a Xilinx Zynq Z-7010 or Z-7020 SoC into a Rasberry-Pi-compatible form factor with 64Mbytes of LPDDR2 SDRAM, four USB ports (in a hub configuration), a 100Mbps Ethernet port, an HDMI port, MIPI DSI and CSI-2 connectors, a PWM digital audio jack, and 128Mbits of Flash memory for configuration and operation.

 

 

 

Trenz ZynqBerry Dev Board.jpg 

 

TE0726 ZynqBerry Dev Board from Trenz

 

 

 

 

 

Hot (and Cold) Stuff: New Spartan-7 1Q Commercial-Grade FPGAs go from -40 to +125°C!

by Xilinx Employee ‎03-22-2017 05:12 PM - edited ‎03-22-2017 05:15 PM (946 Views)

 

There’s a new line in the table for Spartan-7 FPGAs in the FPGA selection guide on page 2 showing an expanded-temperature range option of -40 to +125°C for all six family members. These are “Expanded Temp” -1Q devices. So if you have the need for extreme hi-temp (or low-temp) operation, you might want to check into these devices. Ask your friendly neighborhood Xilinx or Avnet sales rep.

 

 

Spartan-7 Family Table with 1Q devices.jpg
 

 

 

For more information about the Spartan-7 FPGA product family, see:

 

 

 

 

 

 

 

Scary good 3-minute troubleshooting demo of National Instruments’ VirtualBench All-in-One Instrument

by Xilinx Employee ‎03-22-2017 01:40 PM - edited ‎03-23-2017 07:14 AM (773 Views)

 

National Instruments’ (NI’s) VirtualBench All-in-One Instrument, based on the Xilinx Zynq Z-7020 SoC, combines a mixed-signal oscilloscope with protocol analysis, an arbitrary waveform generator, a digital multimeter, a programmable DC power supply, and digital I/O. The PC- or tablet-based user-interface software allows you to make all of those instruments play together as a troubleshooting symphony. That point is made very apparent in this new 3-minute video demonstrating the speed at which you can troubleshoot circuits using all of the VirtualBench’s capabilities in concert:

 

 

 

 

 

For more Xcell Daily blog posts about the NI VirtualBench All-in-One instrument, see:

 

 

 

 

 

For more information about the VirtualBench, please contact NI directly.

 

Arty Z7: Digilent’s new Zynq SoC trainer and dev board—available in two flavors for $149 or $209

by Xilinx Employee ‎03-22-2017 11:18 AM - edited ‎03-22-2017 04:09 PM (3,697 Views)

 

I’ve known this was coming for more than a week, but last night I got double what I expected. Digilent’s Web site has been teasing the new Arty Z7 Zynq SoC dev board for makers and hobbyists for a week—but with no listed price. Last night, prices appeared. That’s right, there are two versions of the board available:

 

  • The $149 Arty Z7-10 based on a Zynq Z-7010 SoC
  • The $209 Arty Z7-20 based on a Zynq Z-7020 SoC

 

 

Digilent Arty Z7.jpg 

 

Digilent Arty Z7 dev board for makers and hobbyists

 

 

 

Other than that, the board specs appear identical.

 

The first thing you’ll note from the photo is that there’s a Zynq SoC in the middle of the board. You’ll also see the board’s USB, Ethernet, Pmod, and HDMI ports. On the left, you can see double rows of tenth-inch headers in an Arduino/chipKIT shield configuration. There are a lot of ways to connect to this board, which should make it a student’s or experimenter’s dream board considering what you can do with a Zynq SoC. (In case you don’t know, there’s a dual-core ARM Cortex-A9 MPCore processor on the chip along with a hearty serving of FPGA fabric.)

 

Oh yeah. The Xilinx Vivado HL Design Suite WebPACK tools? Those are available at no cost. (So is Digilent’s attractive cardboard packaging, according to Arty Z7 Web page.)

 

Although the Arty Z7 board has now appeared on Digilent’s Web site, the product’s Web page says the expected release date is March 27. That’s five whole days away!

 

As they say, operators are standing by.

 

 

Please contact Digilent directly for more Arty Z7 details.

 

 

 

 

You want to learn how to design with and use RF, right? Students from all levels and backgrounds looking to improve their RF knowledge will want to take a look at the new ADALM-PLUTO SDR USB Learning Module from Analog Devices. The $149 USB module has an RF range of 325MHz to 3.8GHz with separate transmit and receive channels and 20MHz of instantaneous bandwidth. It pairs two devices that seem made for each other: an Analog Devices AD9363 Agile RF Transceiver and a Xilinx Zynq Z-7010 SoC.

 

 

 

Analog Devices ADALM-PLUTO SDR USB Learning Module.jpg 

 

 

Analog Devices’ $149 ADALM-PLUTO SDR USB Learning Module

 

 

Here’s an extremely simplified block diagram of the module:

 

 

Analog Devices ADALM-PLUTO SDR USB Learning Module Block Diagram.jpg

 

 

Analog Devices’ ADALM-PLUTO SDR USB Learning Module Block Diagram

 

 

However, the learning module’s hardware is of little use without training material and Analog Devices has already created dozens of online tutorials and teaching materials for this device including ADS-B aircraft position, receiving NOAA and Meteor-M2 weather satellite imagery, GSM analysis, listening to TETRA signals, and pager decoding.

 

 

Digilent says that its new $199.99 Digital Discovery—a low-cost USB instrument that combines a 24-channel, 800Msamples/sec logic analyzer; a 16-bit, 100Msamples/sec digital pattern generator; and a 100mA power supply—“was created to be the ultimate embedded development companion.” Further, “Its features and specifications were deliberately chosen to maintain a small and portable form factor, withstand use in a variety of environments, and keep costs down, while balancing the requirements of operating on USB Power.”

 

(Note: Skip to the bottom of this blog for a limited-time offer. Then come back.)

 

Here’s a photo of the Digital Discovery:

 

 

Digilent Digital Discovery Module.jpg

 

Digilent’s Digital Discovery—a combined 24-channel, 800Msamples/sec logic analyzer and 16-bit, 100Msamples/sec digital pattern generator

 

 

If that form factor looks familiar, you’re probably reminded of the company’s Analog Discovery and Analog Discovery 2 100Msamples/sec USB DSO, logic analyzer, and power supply. (See “$279 Analog Discovery 2 DSO, logic analyzer, power supply, etc. relies on Spartan-6 for programmability, flexibility.) And just like the Analog Discovery modules, the Digilent Digital Discovery is based on a Xilinx Spartan-6 FPGA (an LX25), which becomes pretty clear when you look at the product’s board photo. The Spartan-6 FPGA is right there in the center of the board:

 

 

Digilent Digital Discovery Module Board.jpg

 

Digilent’s Digital Discovery is based on a Xilinx Spartan-6 FPGA

 

 

When I write “based on,” what I mean to say is that Digilent’s IP in the Spartan-6 FPGA pretty much implements the entire low-cost instrument—as clearly shown in the block diagram:

 

 

Digilent Digital Discovery Module Block Diagram.jpg

 

 

Digilent’s Digital Discovery Module Block Diagram

 

 

And what does this $199.99 instrument do, considering that it’s implemented using a low-cost FPGA? Here are the specs (and pretty impressive specs they are):

 

 

  • 24-channel, 800Msamples/sec* digital logic analyzer (1.2…3.3V CMOS)
  • 16-channel, 100Msamples/sec pattern generator (1.2…3.3V)
  • 16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic training applications
  • Two input/output digital trigger signals for linking multiple instruments (1.2…3.3V CMOS)
  • A programmable power supply of 1.2…3.3V/100mA. The same voltage supplies the Logic Analyzer input buffers and the Pattern Generator input/output buffers, for keeping the logic level compatibility with the circuit under test.
  • Digital Bus Analyzers (SPI, I²C, UART, Parallel)

 

*Note: to obtain speeds of 200MS/s and higher, the High Speed Adapter must be used.

 

 

So, you may have noted that asterisk on the logic analyzer's maximum sample rate. You need a Digital Discovery High Speed Adapter to attain the full 800Msamples/sec acquisition rate on the logic analyzer. Normally, that’s another $49.99. However, for the first 100 Digital Discovery buyers, Digilent is throwing in the high-speed adapter in for free.

 

Operators are standing by.

 

 

 

 

 

Image3.jpgAEye is the latest iteration of the eye-tracking technology developed by EyeTech Digital Systems. The AEye chip is based on the Zynq Z-7020 SoC. It’s located immediately adjacent to the imaging sensor, which creates compact, stand-alone systems. This technology is finding its way into diverse vision-guided systems in the automotive, AR/VR, and medical diagnostic arenas. According to EyeTech, the Zynq SoC’s unique abilities allows the company to create products they could not do any other way.

 

With the advent of the reVISION stack, EyeTech is looking to expand its product offerings into machine learning, as discussed in this short, 3-minute video:

 

 

 

 

 

 

For more information about EyeTech, see:

 

 

 

 

Zynq + PYNQ + Python + BNNs: Machine inference does not get any easier… or faster

by Xilinx Employee ‎03-14-2017 03:10 PM - edited ‎03-15-2017 10:25 AM (5,048 Views)

 

Machine learning and machine inference based on CNNs (convolutional neural networks) are the latest way to classify images and, as I wrote in Monday’s blog post about the new Xilinx reVISION announcement, “The last two years have generated more machine-learning technology than all of the advancements over the previous 45 years and that pace isn't slowing down.” (See “Xilinx reVISION stack pushes machine learning for vision-guided applications all the way to the edge.”) The challenge now is to make the CNNs run faster while consuming less power. It would be nice to make them easier to use as well.

 

OK, that’s a setup. A paper published last month at the 25th International Symposium on Field Programmable Gate Arrays titled “FINN: A Framework for Fast, Scalable Binarized Neural Network Inference” describes a method to speed up CNN-based inference while cutting power consumption by reducing CNN precision in the inference machines. As the paper states:

 

…a growing body of research demonstrates this approach [CNN] incorporates significant redundancy. Recently, it has been shown that neural networks can classify accurately using one- or two-bit quantization for weights and activations.  Such a combination of low-precision arithmetic and small memory footprint presents a unique opportunity for fast and energy-efficient image classification using Field Programmable Gate Arrays (FPGAs). FPGAs have much higher theoretical peak performance for binary operations compared to floating point, while the small memory footprint removes the off-chip memory bottleneck by keeping parameters on-chip, even for large networks. Binarized Neural Networks (BNNs), proposed by Courbariaux et al., are particularly appealing since they can be implemented almost entirely with binary operations, with the potential to attain performance in the teraoperations per second (TOPS) range on FPGAs.

 

The paper then describes the techniques developed by the authors to generate BNNs and instantiate them into FPGAs. The results, based on experiment using a Xilinx ZC706 eval kit based on a Zynq Z-7045 SoC, are impressive:

 

When it comes to pure image throughput, our designs outperform all others. For the MNIST dataset, we achieve an FPS which is over 48/6x over the nearest highest throughput design [1] for our SFC-max/LFC-max designs respectively. While our SFC-max design has lower accuracy than the networks implemented by Alemdar et al. for our LFC-max design outperforms their nearest accuracy design by over 6/1.9x for throughput and FPS/W respectively. For other datasets, our CNV-max design outperforms TrueNorth for FPS by over 17/8x for CIFAR-10 / SVHN datasets respectively, while achieving 9.44x higher throughput than the design by Ovtcharov et al., and 2:2x over the fastest results reported by Hegde et al. Our prototypes have classification accuracy within 3% of the other low-precision works, and could have been improved by using larger BNNs.

 

There’s something even more impressive, however. This design approach to creating BNNs is so scalable that it’s now on a low-end platform—the $229 Digilent PYNQ-Z1. (Digilent’s academic price for the PYNQ-Z1 is only $65!) Xilinx Research Labs in Ireland, NTNU (Norwegian U. of Science and Technology), and the U. of Sydney have released an open-source Binarized Neural Network (BNN) Overlay for the PYNQ-Z1 based on the work described in the above paper.

 

According to Giulio Gambardella of Xilinx Reseach Labs, “…running on the PYNQ-Z1 (a smaller Zynq 7020), [the PYNQ-Z1] can achieve 168,000 image classifications per second with 102µsec latency on the MNIST dataset with 98.40% accuracy, and 1700 images per seconds with 2.2msec latency on the CIFAR-10, SVHN, and GTSRB dataset, with 80.1%, 96.69%, and 97.66% accuracy respectively running at under 2.5W.”

 

 

PYNQ-Z1.jpg

 

Digilent PYNQ-Z1 board, based on a Xilinx Zynq Z-7020 SoC

 

 

 

Because the PYNQ-Z1 programming environment centers on Python and the Jupyter development environment, there are a number of Jupyter notebooks associated with this package that demonstrate what the overlay can do through live code that runs on the PYNQ-Z1 board, equations, visualizations and explanatory text and program results including images.

 

There are also examples of this BNN in practical application:

 

 

 

 

For more information about the Digilent PYNQ-Z1 board, see “Python + Zynq = PYNQ, which runs on Digilent’s new $229 pink PYNQ-Z1 Python Productivity Package.

 

 

 

 

The amazing “snickerdoodle one”—a low-cost, single-board computer with wireless capability based on the Xilinx Zynq Z-7010 SoC—is once more available for purchase on the Crowd Supply crowdsourcing Web site. Shipments are already going out to existing backers and, if you missed out on the original crowdsourcing campaign, you can order one for the post-campaign price of $95. That’s still a huuuuge bargain in my book. (Note: There is a limited number of these boards available, so if you want one, now’s the time to order it.)

 

In addition, you can still get the “snickerdoodle black” with a faster Zynq Z-7020 SoC and more SDRAM that also includes an SDSoC software license, all for $195. Finally, snickerdoodle’s creator krtkl has added two mid-priced options: the snickerdoodle prime and snickerdoodle prime LE—also based on Zynq Z-7020 SoCs—for $145.

 

 

Snickerdoodle.jpg

The krtkl snickerdoodle low-cost, single-board computer based on a Xilinx Zynq SoC

 

 

 

Ryan Cousins at krtkl sent me this table that helps explain the differences among the four snickerdoodle versions:

 

 

Snickerdoodle table.jpg

 

 

 

For more information about krtkl’s snickerdoodle SBC, see:

 

 

 

 

 

 

 

 

 

 

Today, Keysight Technologies announced its low-cost InfiniiVision 1000 X-Series oscilloscopes with 50MHz and 100MHz models that start at $449. (Apparently, this is Scope Month and Keysight is giving away 125 DSOs in March—click here for more info.) Even at that low price, these 2-channel 1000 X-Series DSOs are based on Keysight’s high-performance MegaZoom IV custom ASIC technology, which enables a high 50,000 waveforms/sec update rate.

 

 

Keysight 1000 X-Series DSO.jpg

 

 

Keysight 1000 X-Series DSO

 

 

 

These new scopes are intended for students and new users. In fact, the two 50MHz models have “EDU” as a model number prefix. Here’s a table listing the salient features of the four models in the 1000 X-Series family:

 

 

Keysight 1000 X-Series DSO Table.jpg

 

 

 

All four models also operate as a serial protocol analyzer, digital voltmeter, and frequency counter. The EDUX1002G and DSOX1102G models include a frequency response analyzer and function generator.

 

So why are you reading about this very nice, new Keysight instrument in the Xilinx Xcell Daily blog? Well, Keysight supplied one of these new DSOs to my good friend Dave Jones at eevblog.com and of course, he did a teardown; and of course, he found a Xilinx FPGA inside. That's why.

 

Here’s Dave Jones’ 30-minute teardown video of the new Keysight 1000 X-series DSO:

 

 

 

 

 

This DSO features a 2-board construction. The main board is mostly analog and a small daughter board contains the high-speed ADC, the Keysight MegaZoom IV ASIC, an STMicroelectronics SPEAR600 application processor, and a low-end Xilinx Spartan-3E XC3S500E FPGA. That’s a lot of processing power in a very inexpensive DSO family that starts at $450.

 

Here’s Dave’s closeup shot of that digital daughtercard showing the Xilinx FPGA positioned between the SPEAR600 processor and the Keysight MegaZoom IV ASIC (under the finned heat sink):

 

 

 

Keysight 1000 X-Series DSO Digital Daughtercard.jpg 

 

 

Now the Spartan-3E FPGA is not a particularly new device; it was announced more than a decade ago. The Spartan-3E FPGA family was designed from the start to be cost-effective, which is no doubt why Keysight used it in this DSO design. Its appearance in a just-introduced product is a testament to Xilinx’s ongoing commitment to device availability over the long term.

 

 

Please contact Keysight directly for more information about the InfiniiVision 1000 X-Series DSOs.

 

 

 

With a month left in the Indiegogo funding period, the MATRIX Voice open-source voice platform campaign stands at 289% of its modest $5000 funding goal. MATRIX Voice is the third crowdfunding project by MATRIX Labs, based on Miami, Florida. The MATRIX Voice platform is a 3.14-inch circular circuit board capable of continuous voice recognition and compatible with the latest voice-based, cognitive cloud-based services including Microsoft Cognitive Service, Amazon Alexa Voice Service, Google Speech API, Wit.ai, and Houndify. The MATRIX Voice board, based on a Xilinx Spartan-6 LX4 FPGA, is designed to plug directly onto a low-cost Raspberry Pi single-board computer or it can be operated as a standalone board. You can get one of these boards, due to be shipped in May, for as little as $45—if you’re quick. (Already, 61 of the 230 early-bird special-price boards are pledged.)

 

Here’s a photo of the MATRIX Voice board:

 

 

MATRIX Voice board.jpg

 

 

This image of the top of the MATRIX Voice board shows the locations for the seven rear-mounted MEMS microphones, seven RGB LEDs, and the Spartan-6 FPGA. The bottom of the board includes a 64Mbit SDRAM and a connector for the Raspberry Pi board.

 

Because this is the latest in a series of developer boards from MATRIX Labs (see last year’s project: “$99 FPGA-based Vision and Sensor Hub Dev Board for Raspberry Pi on Indiegogo—but only for the next two days!”), there’s already a sophisticated, layered software stack for the MATRIX Voice platform that include a HAL (Hardware Abstraction Layer) with the FPGA code and C++ library, an intermediate layer with a streaming interface for the sensors and vision libraries (for the Raspberry Pi camera), and a top layer with the MATRIX OS and high-level APIs. Here’s a diagram of the software stack:

 

 

MATRIX Voice Software Stack.jpg 

 

And now, who better to describe this project than the originators:

 

 

 

 

 

 

 

 

Innovative Integration’s XA-160M PCIe XMC module suits applications that require high-speed data acquisition and real-time signal processing. The module provides two 16-bit TI ADC16DV160 160Msamples/sec ADCs for high-speed analog input signals and an Analog Devices AD9122 16-bit dual DAC capable of operating at 1200Msamples/sec for driving high-speed analog outputs. The ADCs and DACs are coupled to a Xilinx Artix-7 XC7A200T FPGA (that’s the largest member of the Artix-7 device family with 215,360 logic cells and 740 DSP48 slices). The FPGA also manages 1Gbyte of on-board DDR3 SDRAM and implements PCIe Gen2 x4 and Aurora interfaces for the XMC module’s P15 and P16 connectors respectively. You can use the uncommitted programmable logic on the Artic-7 FPGA for high-speed, real-time signal processing.

 

 

 

Innovative Integration XA-160M XMC Module.jpg

 

Innovative Integration’s XA-160M PCIe XMC Module

 

 

 

Here’s a block diagram that makes everything clear:

 

 

Innovative Integration XA-160M XMC Module Block Diagram.jpg

 

 

Innovative Integration’s XA-160M PCIe XMC Module Block Diagram

 

 

 

Innovative Integrations suggest that you might want to consider using the XA-160M PCIe XMC Module for:

 

 

  • Stimulus/response measurements
  • High-speed servo controls
  • Arbitrary Waveform Generation
  • RADAR
  • LIDAR
  • Optical Servo
  • Medical Scanning

 

 

You can customize the logic implemented in the Artix-7 FPGA using VHDL and MathWorks’ MATLAB using the company’s FrameWork Logic toolset. The MATLAB BSP supports real-time, hardware-in-the- loop development using the graphical Simulink environment along with the Xilinx System Generator for DSP, which is part of the Xilinx Vivado Design Suite.

 

Please contact Innovative Integrations directly for more information about the XA-160M PCIe XMC Module.

 

 

 

Red Pitaya has been offering its namesake, Zynq-SoC-based, open instrumentation platform as a packaged STEMlab with analog and digital probes, power supply and enclosure. The STEMlab prices range from €249.00 to €499.00 depending on options. To support this hardware, Red Pitaya is distributing apps and the latest turns the STEMlab into a combo 40MHz digital oscilloscope and 50MHz signal generator.

 

Here are the scope specs:

 

 

Red Pitaya STEMlab Scope Specs.jpg

 

 

Red Pitaya STEMlab DSO Specs

 

 

 

And here are the signal generator specs:

 

 

 

Red Pitaya STEMlab Signal Generator Specs.jpg

 

 

Red Pitaya STEMlab Signal Generator Specs

 

 

 

For more articles about the Zynq-based Red Pitaya, see:

 

 

 

The Koheron SDK and Linux distribution, based on Ubuntu 16.04, allows you to prototype working instruments for the Red Pitaya Open Instrumentation Platform, which is based on a Xilinx Zynq All Programmable SoC. The Koheron SDK outputs a configuration bitstream for the Zynq SoC along with the requisite Linux drivers, ready to run under the Koheron Linux Distribution. You build the FPGA part of the Zynq SoC design by writing the code in Verilog using the Xilinx Vivado Design Suite and assembling modules using TCL.

 

The Koheron Web site already includes several instrumentation examples based on the Red Pitaya including an ADC/DAC exerciser, a pulse generator, an oscilloscope, and a spectrum analyzer. The Koheron blog page documents several of these designs along with many experiments designed to be conducted using the Red Pitaya board. If you’re into Python as a development environment, there’s a Koheron Python library as well.

 

There’s also a quick-start page on the Koheron site if you’re in a hurry.

 

 

 

Red Pitaya Open Instrumentation Platform small.jpg 

 The Red Pitaya Open Instrumentation Platform

 

 

 

For more articles about the Zynq-based Red Pitaya, see:

 

 

 

 

Last September, Xilinx announced the six members of the 28nm Spartan-7 FPGA family for “cost-sensitive” designs (that’s marketing-speak for “low-cost”) and for designs that require small-footprint devices. (The two smallest members of the Spartan-7 family will be offered in 8x8mm CPGA196 packages with 100 user I/O pins.)

 

 

Spartan-7 FPGA Family Table v2.jpg

 

 

 

There’s a new 15-minute video with a quick technical overview of the Spartan-7 family:

 

 

 

 

And you can download the 50-page Advance Product Specification here.

 

A Very Short Conversation with Ximea about Subminiature Video Cameras and Very Small FPGAs

by Xilinx Employee ‎02-02-2017 01:00 PM - edited ‎02-02-2017 09:54 PM (2,347 Views)

 

Yesterday at Photonics West, my colleague Aaron Behman and I stopped by the Ximea booth and had a very brief conversation with Max Larin, Ximea’s CEO. Ximea makes a very broad line of industrial and scientific cameras and a lot of them are based on several generations of Xilinx FPGAs. During our conversation, Max removed a small pcb from a plastic bag and showed it to us. “This is the world’s smallest industrial camera,” he said while palming a 13x13mm board. It was one of Ximea’s MU9 subminiature USB cameras based on a 5Mpixel ON Semiconductor (formerly Aptina) MT9P031 image sensor. Ximea’s MU9 subminiature camera is available as a color or monochrome device.

 

Here’s are front and back photos of the camera pcb:

 

 

Ximea MU9 Subminiature Camera.jpg

 

Ximea 5Mpixel MU9 subminiature USB camera

  

 

As you can see, the size of the board is fairly well determined by the 10x10mm image sensor, its bypass capacitors, and a few other electronic components mounted on the front of the board. Nearly all of the active electronics and the camera’s I/O connector are mounted on the rear. A Cypress CY7C68013 EZ-USB Microcontroller operates the camera’s USB interface and the device controlling the sensor is a Xilinx Spartan-3 XC3S50 FPGA in an 8x8mm package. FPGAs with their logic and I/O programmability are great for interfacing to image sensors and for processing the video images generated by these sensors.

 

Our conversation with Max Larin at Photonics West got me to thinking. I wondered, “What would I use to design this board today?” My first thought was to replace both the Spartan-3 FPGA and the USB microcontroller with a single- or dual-core Xilinx Zynq SoC, which can easily handle all of the camera’s functions including the USB interface, reducing the parts count by one “big” chip. But the Zynq SoC family’s smallest package size is 13x13mm—the same size as the camera pcb—and that’s physically just a bit too large.

 

The XC3S50 FPGA used in this Ximea subminiature camera is the smallest device in the Spartan-3 family. It has 1728 logic cells and 72Kbits of BRAM. That’s a lot of programmable capability in an 8x8mm package even though the Spartan-3 FPGA family first appeared way back in 2003. (See “New Spartan-3 FPGAs Are Cost-Optimized for Design and Production.”)

 

There are two newer Spartan FPGA families to consider when creating a design today, Spartan-6 and Spartan-7, and both device families include multiple devices in 8x8mm packages. So I decided see how much I might pack into a more modern FPGA with the same pcb real-estate footprint.

 

The simple numbers from the data sheets tell part of the story. A Spartan-3 XC3S50 provides you with 1728 logic cells, 72Kbits of BRAM, and 89 I/O pins. The Spartan-6 XCSLX4, XC6SLX9, and XCSLX16 provide you with 3840 to 14,579 logic cells, 216 to 576Kbits of BRAM, and 106 I/O pins. The Spartan-7 XC7S6 and XC7S15 provide 6000 to 12,800 logic cells, 180 to 360Kbits of BRAM, and 100 I/O pins. So both the Spartan-6 and Spartan-7 FPGA families provide nice upward-migration paths for new designs.

 

However, the simple data-sheet numbers don’t tell the whole story. For that, I needed to talk to Jayson Bethurem, the Xilinx Cost Optimized Portfolio Product Line Manager, and get more of the story. Jayson pointed out a few more things.

 

First and foremost, the Spartan-7 FPGA family offers a 2.5x performance/watt improvement over the Spartan-6 family. That’s a significant advantage right there. The Spartan-7 FPGAs are significantly faster than the Spartan-6 FPGAs as well. Spartan-6 devices in the -1L speed grade have a 250MHz Fmax versus 464MHz for Spartan-7 -1 or -1L parts. The fastest Spartan-6 devices in the -3 speed grade have an Fmax of 400MHz (still not as fast as the slowest Spartan-7 speed grade) and the fastest Spartan-7 FPGAs, the -2 parts, have an Fmax of 628MHz. So if you feel the need for speed, the Spartan-7 FPGAs are the way to go.

 

I’d be remiss not to mention tools. As Jayson reminded me, the Spartan-7 family gives you entrée into the world of Vivado Design Suite tools. That means you get access to the Vivado IP catalog and Vivado’s IP Integrator (IPI) with its automated integration features. These are two major benefits.

 

Finally, some rather sophisticated improvements to the Spartan-7 FPGA family’s internal routing architecture means that the improved placement and routing tools in the Vivado Design Suite can pack more of your logic into Spartan-7 devices and get more performance from that logic due to reduced routing congestion. So directly comparing logic cell numbers between the Spartan-6 and Spartan-7 FPGA families from the data sheets is not as exact a science as you might assume.

 

The nice thing is: you have plenty of options.

 

 

For previous Xcell Daily blog posts about Ximea industrial and scientific cameras, see:

 

 

 

 

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About the Author
  • Be sure to join the Xilinx LinkedIn group to get an update for every new Xcell Daily post! ******************** Steve Leibson is the Director of Strategic Marketing and Business Planning at Xilinx. He started as a system design engineer at HP in the early days of desktop computing, then switched to EDA at Cadnetix, and subsequently became a technical editor for EDN Magazine. He's served as Editor in Chief of EDN Magazine, Embedded Developers Journal, and Microprocessor Report. He has extensive experience in computing, microprocessors, microcontrollers, embedded systems design, design IP, EDA, and programmable logic.