When the engineering team at MADV Technology set out to develop the Madventure 360—the world’s smallest, lightest, and thinnest consumer-grade, 360° 4K video camera—in late 2015, it discovered that an FPGA was the only device capable of meeting all of their project goals. As a result, the Madventure camera relies on a Xilinx Spartan-6 FPGA to stitch and synchronize the video streams from two image sensors (one aimed to the front, one aimed to the back) while also performing additional image processing. The tiny, palm-sized camera measures only 3.1x2.6 inches and is only 0.9 inches thick. It sells on Amazon at the moment for $309.99, complete with selfie stick and mini tripod.
MADV Madventure 360° video camera
Now you can hear a little about how MADV Technology created this tiny video wonder in this new Powered by Xilinx video:
Photonfocus has just introduced another industrial video camera in its MV1 industrial camera line—the MV1-D1280-L01-1280-G2 1280x1024-pixel, 85fps (948fps in burst mode), with a GigE interface—which implements all standard features of the MV1 platform as well as burst mode, MROI (multiple regions of interest), and binning. In burst mode, the camera’s internal 2Gbit burst memory can store image sequences for subsequent analysis. The amount of storage depends on image resolution: 250msec at 1024x124 pixels, 1000msec at 512x512 pixels. The maximum amount of stored video also varies with the size of the specified ROI.
The MV1-D1280-L01-1280-G2 1280x1024-pixel, 85fps (948fps in burst mode) industrial video camera with a GigE interface
Like many of its existing industrial video cameras, Photonfocus’ MV1-D1280-L01-1280-G2 is based on a platform design that uses a Xilinx Spartan-6 FPGA for a foundation. Use of the Spartan-6 FPGA permitted Photonfocus to create an extremely flexible vision-processing platform that serves as a common hardware foundation for several radically different types of rugged, industrial cameras in multiple camera lines. These cameras use very different imaging sensors to meet a wide variety of application requirements. The different sensors have very different sensor interfaces, which is why using the Spartan-6 FPGA—an interfacing wizard if there ever was one—as a foundation technology is such a good idea.
Here are some of the other Xilinx-based Photonfocus cameras covered previously in Xcell Daily:
HuMANDATA has introduced its EDX-303 series of FPGA dev boards featuring the three largest members of the new Xilinx Spartan-7 FPGAs: the S50T, S75T, and S100T. One other notable device on the board: a nonvolatile Everspin MR2A16AMA35 4Mbit MRAM (magnetic RAM) directly controlled by the Spartan-7 FPGA.
The boards all measure 53x54mm and share a common block diagram:
HuMANDATA EDX-303 dev board block diagram
Here’s a photo of the board:
HuMANDATA EDX-303 dev board for the three largest Spartan-7 FPGAs
Please contact HuMANDATA directly for more information about the EDX-303 dev board series.
Bitmain manufactures Bitcoin, Litecoin, and other cryptocurrency mining machines and currently operates the world’s largest cryptocurrency mines. The company’s latest-generation Bitcoin miner, the Antminer S9, incorporates 189 of Bitmain’s 16nm ASIC, the BM1387, which performs the Bitcoin hash algorithm at a reate of 14 TeraHashes/sec. (See “Heigh ho! Heigh ho! Bitmain teams 189 bitcoin-mining ASICs with a Zynq SoC to create world's most powerful bitcoin miner.”) The company also uses one Zynq Z-7010 SoC to control those 189 hash-algorithm ASICs.
Bitmain’s Antminer S9 Bitcoin Mining Machine uses a Zynq Z-7010 SoC as a main control processor
The Powered by Xilinx program has just published a 3-minute video containing an interview with Yingfei Li, Bitmain’s Marketing Director, and Wenguo Zhang, Bitmain’s Hardware R&D Director. In the video, Zhang explains that the Zynq Z-7010 solved multiple hidden problems with the company’s previous-generation control panel, thanks to the Zynq SoC’s dual-core Arm Cortex-A9 MPCore processor and the on-chip programmable logic.
Due to the success that Bitmain has had with Xilinx Zynq SoCs in it’s Antminer S9 Bitcoin mining machine, the company is now exploring the use of Xilinx 20nm and 16nm devices (UltraScale and UltraScale+) for future, planned AI platforms and products.
Need a tiny-but-powerful SOM for your next embedded project? The iWave iW-RainboW-G28M SOM based on a Xilinx Zynq Z-7007S, Z-7014S, Z-7010, or Z-7020 SoC is certainly tiny—it’s a 67.6x37mm plug-in SoDIMM—and with one or two Arm Cortex A9 MPCore processors, 512Mbytes of DDR3 SDRAM, 512Mbytes of NAND Flash, Gigabit Ethernet and USB 2.0 ports, and an optional WiFi/Bluetooth module it certainly qualifies as powerful and it’s offered in an industrial temp range (-40°C to +85°C).
iWave’s iW-RainboW-G28M SoDIMM SOM is based on any one of four Xilinx Zynq SoCs
iWave’s SOM design obviously takes advantage of the pin compatibility built into the Xilinx Zynq Z-7000S and Z-7000 device families.
Please contact iWave directly for more information about the iW-RainboW-G28M SoDIMM SOM.
Yesterday’s blog post titled “Dialog Semi offers array of low-cost power solutions for Zynq UltraScale+ MPSoCs (and Spartan-7 FPGAs too!)” ended with this sentence:
Dialog Semiconductor’s app note, AN-PM-096, titled “Power Solutions for Xilinx Spartan-7 Devices” has a full discussion of this topic and provides a reference design for the DA9062 PMIC that consumes a mere 420mm2 (20x21mm) of pcb area.
Here’s how the DA9062 PMIC’s four internal buck regulators and four internal LDO regulators match up to the power requirements of a Spartan-7 FPGA:
And here’s the pcb footprint for the DA9062 reference design:
As noted by Xilinx Senior Tech Marketing Manager for Analog and Power Delivery Cathal Murphy, the DA9062 PMIC makes a good match for the Xilinx Spartan-6 FPGA family as well.
One of life’s realities is that the most advanced semiconductor devices—including the Xilinx Zynq UltraScale+ MPSoCs—require multiple voltage supplies for proper operation. That means that you must devote a part of the system engineering effort for a product based on these devices to the power subsystem. Put another way, it’s been a long, long time since the days when a single 5V supply and a bypass capacitor were all you needed. Fortunately, there’s help. Xilinx has a number of vendor partners with ready, device-specific power-management ICs (PMICs). Case in point: Dialog Semiconductor.
If you need to power a Zynq UltraScale+ ZU3EG, ZU7EV, or ZU9CG MPSoC, you’ll want to check out Dialog’s App Note AN-PM-095 titled “Power Solutions for Xilinx Zynq Ultrascale+ ZU9EG.” This document contains reference designs for cost-optimized, PMIC-based circuits specifically targeting the power requirements for Zynq UltraScale+ MPSoCs. According to Xilinx Senior Tech Marketing Manager for Analog and Power Delivery Cathal Murphy, Dialog Semi’s PMICs can be used for low-cost power-supply designs because they generate as many as 12 power rails per device. They also switch at frequencies as high as 3MHz, which means that you can use smaller, less expensive passive devices in the design.
It also means that your overall power-management design will be smaller. For example, Dialog Semi’s power-management ref design for a Zynq UltraScale+ ZU9 MPSoC requires only 1.5in2 of board space—or less for smaller devices in the MPSoC family.
You don’t need to visualize that in your head. Here’s a photo and chart supplied by Cathal:
The Dialog Semi reference design is hidden under the US 25-cent piece.
As the chart notes, these Dialog Semi PMICs have built in power sequencing and can be obtained preprogrammed for Zynq-specific power sequences from distributors such as Avnet.
Cathal also pointed out that Dialog Semi has long been supplying PMICs to the consumer market (think smartphones and tablets) and that the power requirements for Zynq UltraScale+ MPSoCs map well into the existing capabilities of PMICs designed for this market, so you reap the benefit of the company’s volume manufacturing expertise.
Late last week, Avnet announced that it’s now offering the Aaware Sound Capture Platform paired with the MiniZed Zynq SoC development platform as a complete dev kit for voice-based cloud services including Amazon Alexa and Google Home. It’s listed on the Avnet site for $198.99. Avnet and Aaware are demonstrating the new kit at CES 2018, being held this week in Las Vegas. You’ll find them at the Eureka Park booth #50212 in the Sands Expo.
The Aaware Sound Capture Platform coupled to a Zynq-based Avnet MiniZed dev board
The Aaware Sound Capture Platform couples as many as 13 MEMS microphones (you can use fewer in a 1D linear or 2D array) with a Xilinx Zynq Z-7010 SoC to pre-filter incoming voice, delivering a clean voice data stream to local or cloud-based voice recognition hardware. The system has a built-in wake word (like “Alexa” or “OK, Google”) that triggers the unit’s filtering algorithms.
Avnet’s MiniZed dev board is usually based on a single-core Zynq 7Z007S but the MiniZed board included in this kit is actually based on a dual-core Zynq Z-7010 SoC. This board offers you outstanding wireless I/O in the form of a WiFi 802.11b/g/n module and a Bluetooth 4.1 module.
For more information about the Aaware Sound Capture Platform, see:
My good friend Jack Ganssle has long published The Embedded Muse email newsletter and the January 2, 2018 issue (#341!) includes an extensive review of the new $759, Zynq-based Siglent SDS1204X-E 4-channel DSO. Best of all, he’s giving one of these bad boys away at the end of January. (Contest details below.)
Siglent’s Zynq-based SDS1204X-E 4-channel DSO. Photo credit: Jack Ganssle
The Siglent SDS1204X-E is the 4-channel version of the Siglent SDS1202X-E that EEVblog’s Dave Jones tore down last April. (See “Dave Jones tears down the new, <$400, Zynq-powered, Siglent SDS1202X-E 2-channel, 200MHz, 1Gsamples/sec DSO.”) I personally bought one of those scopes and I can attest to it’s being one sweet instrument. You should read Jack’s detailed review on his Web site, but here’s his summary:
“I'm blown away by the advanced engineering and quality of manufacturing exhibited by this and some other Chinese test equipment. Steve Leibson wrote a piece about how the unit works, and it's clear that the innovation and technology in this unit are world-class.”
In my own review of the Siglent SDS1202X-E last November, I wrote:
“Siglent’s SDS-1202X-E and SDS-1104X-E DSOs once again highlight the Zynq SoC’s flexibility and capability when used as the foundation for a product family. The Zynq SoC’s unique combination of a dual-core Arm Cortex-A9 MPCore processing subsystem and a good-sized chunk of Xilinx 7 series FPGA permits the development of truly high-performance platforms.”
Last April, I wrote:
“The new SDS1000X-E DSO family illustrates the result of selecting a Zynq SoC as the foundation for a system design. The large number of on-chip resources permit you to think outside of the box when it comes to adding features. Once you’ve selected a Zynq SoC, you no longer need to think about cramming code into the device to add features. With the Zynq SoC’s hardware, software, and I/O programmability, you can instead start thinking up new features that significantly improve the product’s competitive position in your market.
“This is precisely what Siglent’s engineers were able to do. Once the Zynq SoC was included in the design, the designers of this entry-level DSO family were able to think about which high-performance features they wished to migrate to their new design.”
All of that is equally true for the Siglent SDS1204X-E 4-channel DSO, which is further proof of just how good the Zynq SoC is when used as a foundation for an entire product-family.
Now if you want to win the Siglent SDS1204X-E 4-channel DSO that Jack’s giving away at the end of January, you first need to subscribe to The Embedded Muse. The subscription is free, Jack’s an outstanding engineer and a wonderful writer, and he’s not going to sell or even give your email address to anyone else so consider the Embedded Muse subscription a bonus for entering the drawing. After you subscribe, you can enter the contest here. (Note: It’s Jack’s contest, so if you have questions, you need to ask him.)
How do you get reliable, far-field voice recognition; robust, directional voice recognition in the presence of strong background noise; and multiple wake words for voice-based cloud services such as Amazon’s Alexa and Google Home? Aaware has an answer with its $199, Zynq-based Far-Field Development Platform. (See “13 MEMS microphones plus a Zynq SoC gives services like Amazon’s Alexa and Google Home far-field voice recognition clarity.”) A new Powered by Xilinx Demo Shorts video gives you additional info and another demo. (That’s a Zynq-based krtkl snickerdoodle processing board in the video.)
Vivado 2017.4 is now available. Download it now to get these new features (see the release notes for complete details):
Download the new version of the Vivado Design Suite HLx editions here.
There are a few Xilinx-based dev boards and instruments on sale right now at Digilent. You’ll find them on the “End of the Year Sale” Web page:
If you were considering one of these Digilent products, now’s probably the time to buy.
RHS Research’s PicoEVB FPGA dev board based on an Artix-7 A50T FPGA snaps into an M.2 2230 key A or E slot, which is common in newer laptops. The board measures 22x30mm, which is slightly larger than the Artix-7 FPGA and configuration EEPROM mounted on one side of the board. It has a built-in JTAG connection that works natively with Vivado.
Here’s a photo that shows you the board’s size in relation to a US 25-cent piece:
Even though the board itself is small, you still get a lot of resources in the Artix-7 A50T FPGA including 52,160 logic cells, 120 DSP48 slices, and 2.7Mbits of BRAM.
Here’s a block diagram of the board:
The PicoEVB is available on Crowd Supply. The project was funded at the end of October.
Fairwave’s XTRX, a “truly” embedded SDR (software-defined radio) module now up as a Crowd Supply crowdfunding project, manages to pack an entire 2x2 MIMO SDR with an RF tuning range of 30MHz to 3.8GHz into a diminutive Mini PCIe format (30x51mm) by pairing Lime Microsystems’ LMS7002M 2nd-generation field-programmable RF Transceiver with a Xilinx Artix-7 35T FPGA. As of today, the project is 84% funded with 27 days left in the funding period and 317 pledges. The industry-standard Mini PCIe form factor allws you to embed the XTRX SDR module just about anywhere. According to Fairwaves, the XTRX is compatible with all of the popular SDR development tool suites.
Fairwaves’ XTRX 2x2 MIMO SDR Mini PCIe Module
Here’s a block diagram of the XTRX SDR module:
Fairwaves’ XTRX 2x2 MIMO SDR Module Block Diagram
Perhaps even more interesting, here’s a comparison chart that Fairwaves developed to point out the advantages of the XTRX SDR module:
Need something more complex than a 2x2 MIMO arrangement? There’s a PCIe Octopack carrier board that accepts as many as eight XTRX Mini PCIe modules (four on each side) creating a 16x16 MIMO SDR and you can synchronize multiple Octopack boards to create massive-MIMO configurations.
Fairwaves’ XTRX 2x2 MIMO SDR Module Octopack
More information about the XTRX is available on the Crowd Supply project page.
In an article published in EETimes today titled “Programmable Logic Holds the Key to Addressing Device Obsolescence,” Xilinx’s Giles Peckham argues that the use of programmable devices—such as the Zynq SoCs, Zynq UltraScale+ MPSoCs, and FPGAs offered by Xilinx—can help prevent product obsolescence in long-lived products designed for industrial, scientific, and military applications. And that assertion is certainly true. But in this blog, I want to highlight the response by a reader using the handle MWagner_MA who wrote:
“Given the pace of change in FPGA's, I don't know if an FPGA will be a panacea for chip obsolescence issues. However, when changes in system design occur for hooking up new peripherals to a design off board, FPGA's can extend the life of a product 5+ years assuming you can get board-compatible FPGA's. Comm channels are what come to mind. If you use the same electrical interface but have an updated protocol, programmable logic can be a solution. Another solution is that when devices on SPI or I2C busses go obsolete, FPGA code can get updated to accomodate, even changing protocol if necessary assuming the right pins are connected at the other chip (like an A/D).”
MWagner_MA’s response is nuanced and tempered with obvious design experience. However, I will need to differ with the comment that the pace of change in FPGAs means something significant within the context of product obsolescence. Certainly FPGAs go obsolete, but it takes a long, long time.
Case in point:
I received an email just today from Xilinx about this very topic. (Feel free to insert amusement here about Xilinx’s corporate blogger being on the company’s promotional email list.) The email is about Xilinx’s Spartan-6 FPGAs, which were first announced in 2009. That’s eight or nine years ago. Today’s email states that Xilinx plans to ship Spartan-6 devices “until at least 2027.” That’s another nine or ten years into the future for a resulting product-line lifespan of nearly two decades and that’s not all that unusual for Xilinx parts. In other words, Xilinx FPGAs are in another universe entirely when compared to the rapid pace of obsolescence for semiconductor devices like PC and server processors. That’s something to keep in mind when you’re designing products destined for a long life in the field.
If you want to see the full long-life story for the Spartan-6 FPGA family, click here.
TSN (time-sensitive networking) is a set of evolving IEEE standards that support a mix of deterministic, real-time and best-effort traffic over fast Ethernet connections. The TSN set of standards is bocming increasingly important in many industrial networking sutuations, particularly for IIoT (the Industrial Internet of Things). SoC-e has developed TSN IP that you can instantiate in Xilinx All Programmable devices. (Because the standards are still evolving, implementing the TSN hardware in reprogrammable hardware is a good idea.)
In particular, the company offers the MTSN (Multiport TSN Switch IP Core) IP core, which provides precise time synchronization of network nodes using synchronized, distributed local clocks with a reference and IEEE 802.1Qbv for enhanced traffic scheduling. You can currently instantiate the SoC-e core on all of the Xilinx 7 series devices (the Zynq SoC and Spartan-7, Artix-7, Kintex-7, and Virtex-7 FPGAs), Virtex and Kintex UltraScale devices, and all UltraScale+ devices (the Zynq UltraScale+ MPSoCs and Virtex and Kintex UltraScale+ FPGAs).
Here’s a short three-and-a-half minute video explaining TSN and the SoC-e MSTN IP:
SEGGER has added the RISC-V processor to its list of more than 80 ports for the company’s embOS RTOS, which guarantees 100% deterministic, real-time operation for any embedded device. The embOS RTOS is fully compliant with the MISRA-C:2012 standard, making it suitable for demanding automotive and high-integrity applications. The RISC-V embOS port comes with a BSP (board support package) for Digilent’s $99 ARTY evaluation board—based on a Xilinx Artix-7 A35T FPGA—providing a straightforward getting-started experience with SEGGER software on RISC-V. In support of the RTOS, SEGGER offers emWin to construct user interfaces, emFile file system, emSSL, emSSH and emSecure to secure internet communications, cryptographic and security libraries for encryption, code signing and authentication (digital signatures), embOS/IP, emModbus, emUSB-Host and emUSB-Device communication stacks for Internet and industrial applications, and emLoad to enable firmware updates from portable storage or delivered over the air.
Digilent’s $99 Arty dev board is based on a Xilinx Artix-7 FPGA
For more information about instantiating the RISC-V processor architecture in Xilinx All Programmable devices, see:
Last month, Dave Jones tore down yet another low-end DSO—the Uni-T Ultra Phosphor UPO2104CS 4-channel, 100MHz, 1Gsamples/sec scope—on his EEVBlog Web site and he found a Xilinx Spartan-6 FPGA inside. (It appears in the video at 22:00.) The Spartan-6 LX45 FPGA manages the DSO’s sample memories which include a fast SRAM and an SDRAM.
Uni-T Ultra Phosphor UPO2104CS 4-channel, 100MHz, 1Gsamples/sec DSO
Here’s a photo of the Spartan-6 LX45 FPGA on the DSO’s main board.
Spartan-6 FPGA detail from Uni-T Ultra Phosphor UPO2104CS DSO
(Photo courtesy of Dave Jones)
As with many DSOs that Dave Jones has torn down, the Spartan-7 FPGA manages the flow of captured data from the DSO’s 1Gsample/sec ADC and through the DSO’s sample memory. As a result, the scope can capture 30,000 waveforms/sec and it can capture as many as 65,000 waveform frames in its SDRAM capture buffer. In the image above, the length-matched signal lines emerging from the top of the Spartan-6 FPGA lead to the fast SRAM capture memory and the length-matched lines emerging from the bottom of the FPGA lead to the SDRAM waveform memory.
Here’s Jones’ 33-minute teardown video. The Spartan-6 FPGA appears at around 22:00 in the video.
Uni-T’s UPO2104CS DSO currently sells for $538.88 on Banggood.com.
Earlier this month, Spectrum Instrumentation announced the first members of a new series of high-speed, multichannel digitizers based on its new M2p PCIe platform board, which in turn is based on a Xilinx Artix-7 A75T FPGA. According to the announcement, the M2p PCIe platform board will serve as the base for all of the company’s future products, including the initial series of thirteen new M2p.59xx digitizer boards with digitizing speeds of 20, 40, 80, or 125Msamples/sec with 1, 2, 4, or 8 16-bit analog input channels (with separate ADCs for each channel) using one or two mezzanine modules in the company’s new 59 module family. There’s also 1Gbyte of on-board SDRAM capable of storing 512M samples (several seconds of real-time storage for digitized signals).
Spectrum Instrumentation’s new M2p.59xx high-speed digitizer family is based on the Xilinx Artix-7 FPGA
This modular design immediately creates 20 new digitizers in the product family. Another mezzanine board called star-Hub allows you to synchronize as many as sixteen M2p.59xx digitizer boards. Oliver Rovini, Spectrum’s CTO, says that “…the new units will smoothly replace all our current 12, 14 and 16-bit models giving our existing customers an easy upgrade path with a lot of technical advantages.” More models based on the M2p PCIe platform will be announced next year and might include AWGs (arbitrary waveform generators) and digital-I/O boards in addition to high-speed analog digitizers. Target applications for Spectrum’s new digitizer board family include ultrasound, laser, lidar, radar, automotive, and big physics experiments.”
The on-board Artix-7 FPGA implements the M2p board’s PCIe Gen1 x4 interface, the interfaces to the mezzanine boards, and multiple intelligent acquisition modes including multiple recording for segmented acquisition, gated sampling for time-specific acquisition, and an ABA mode that combines chart recorder and fast-acquisition modes. The Artix-7 FPGA also implements multiple trigger inputs, trigger outputs, status outputs, and synchronous digital inputs as well as time stamping of the digitized signals.
Using an All Programmable device, specifically the Artix-7 FPGA, allowed Spectrum to develop a truly flexible platform that can accommodate just about any requirement in the target markets. The device’s reprogrammable I/O accommodates a wide range of ADC interfaces and can just as easily handle the DACs needed to create AWG mezzanine modules. The same is true for implementing the M2p board’s PCIe x4 interface. The device’s programmable logic allows the company to develop all sorts of processing and control IP suitable for tailoring the board to a wide range of applications without making changes to the BOM.
Finally, the company’s new video about this product line (see below) notes that the company supports its products with service and repair for 15 years after introduction. Xilinx’s long-term support for its All Programmable devices makes this sort of end-product support possible. If you closely analyze the wording in Spectrum Instrumentation’s announcement, the company has bet its future on the Artix-7 FPGA. It takes a powerful, flexible, reliable foundation technology to make a bet like that.
Here’s a 4-minute video from Spectrum Instrumentation detailing the features of the new M2p.59xx product line:
Over at EEVBlog, Dave jones has just published a teardown of the brand new Siglent SDS-1104X-E 4-channel DSO. This $499 digital scope features four 100MHz channels and a 1Gsample/sec maximum data rate. It has two ADCs inside, so the data rate only falls to 500Msample/sec when all four channels are enabled. Like it’s sibling, the SDS-1202X-E (see “Siglent 200MHz, 1Gsample/sec SDS1000X-E Entry-Level DSO family with 14M sample points is based on Zynq SoC” and “Dave Jones tears down the new, <$400, Zynq-powered, Siglent SDS1202X-E 2-channel, 200MHz, 1Gsamples/sec DSO”), the Siglent SDS-1104X-E is based on a Xilinx Zynq SoC for its foundation architecture. (According to a posting on the EEVBlog forum and data on the siglent.com Web site, there’s also a 200MHz version of the DSO: the SDS-1204X-E.) In fact, the photo of the DSO’s main board shows little more than the four analog front ends (lower left), the two ADCs (immediately above the analog front ends), the Zynq SoC (upper right under the heat sink), and three SDRAM chips that flank the Zynq SoC.
Although he didn’t remove the heat sink in this teardown video, Dave explains that Siglent told him there’s a Zynq SoC under the heat sink. The SDS-1202X-E used a Zynq Z-7020 SoC. We don’t know from Dave’s video which Zynq SoC Siglent’s engineers used in the SDS-1104X-E design. However, this is an all-new board design for Siglent with two ADCs instead of one. Even so, the previously used Zynq Z-7020 may well be able to handle the extra few differential-pair I/O lines from the second ADC and, because the SDS-1104X-E is a 1Gsamples/sec DSO, the total data rate with all four channels enabled is 2Gsamples/sec, which is the same as the SDS-1202X-E DSO’s maximum data rate.
Siglent’s SDS-1202X-E and SDS-1104X-E DSOs once again highlight the Zynq SoC’s flexibility and capability when used as the foundation for a product family. The Zynq SoC’s unique combination of a dual-core Arm Cortex-A9 MPCore processing subsystem and a good-sized chunk of Xilinx 7 series FPGA permits the development of truly high-performance platforms.
Here’s Dave’s teardown video for your edification:
Back in August, when Opal Kelly announced the SYZYGY high-speed mezzanine bus specification, you just knew there would be a board coming soon with SYZYGY support. That’s board’s now here; it’s called the SYZYGY Brain-1; it’s based on the Xilinx Zynq Z-7012 SoC; and it’s available through Crowd Supply for $299.95. In addition to the Zynq Z-7012 SoC, the board includes 1Gbyte of DDR3 SDRAM, three SYZYGY Standard ports, one SYZYGY Transceiver port, a USB Type-C OTG port, a Gigabit Ethernet port, and an SD card slot. A Standard SYZYGY connector offers 8 differential-pair signals (or 16 single-ended signals) plus another 12 single-ended, impedance-controlled signals. The Transceiver SYZYGY connector offers four lanes of Gigabit-class transceiver connections plus additional 18 single-ended signals. The SYZYGY specification and the Brain-1 board obviously make good use of the Zynq Z-7012 SoC's excellent programmable connectivity and high-speed SerDes ports.
Opal Kelly SYZYGY Brain-1 based on a Xilinx Zynq Z-7012 SoC
Now a brand new mezzanine bus interface standard is not very helpful unless there are mezzanine boards available, so Opal Kelly has developed a few:
Note, for more information about Opal Kelly’s SYZYGY specification, see “Is Opal Kelly’s SYZYGY the new "Goldilocks" high-speed, mezzanine-board and peripheral I/O standard?”
Back in August, I wrote about a series of GigE 3D imaging sensors based on Spartan-6 FPGAs from Carnegie Robotics. (See “Carnegie Robotics’ FPGA-based GigE 3D cameras help robots sweep mines from a battlefield, tend corn, and scrub floors.”) That blog post mentioned that Carnegie Robotics had teamed with GPS maker Swift Navigation to work on autonomous robots that would employ the 3D and positioning-system sensors from the two companies. That post also mentioned that the photo of Swift Navigation’s centimeter-accurate Piksi Multi multi-band, multi-constellation GNSS (global navigation satellite system) receiver clearly showed that the receiver is based on a Zynq Z-7020 SoC.
Now, Swift Navigation has just appeared in the latest “Powered by Xilinx” video. In this video, Swift Navigation’s CEO and Founder Timothy Harris describes his company’s use of the Zynq SoC in the Piksi Multi. The Zynq SoC’s programmable logic processes the incoming signals from multiple global-positioning satellite constellations on multiple frequencies and performs measurements on those signals that is normally performed by dedicated hardware. Then the Zynq SoC’s dual-core Arm Cortex-A9 MPCore processor calculates a physical position from those measurements.
The advantages that hardware and software programmability confer on Swift Navigation’s Piksi Multi includes the ability to quickly adapt the GNSS module for specific customer requirements and the ability to update, upgrade, and add features to the module via over-the-air transmissions. These capabilities give Swift Navigation a competitive advantage over competitive designs that employ dedicated hardware.
Here’s the video:
Digilent has announced a major upgrade to the Zynq-based Zybo dev board, now called the Zybo Z7. The original board was based on a Xilinx Zynq Z-7010 SoC with the integrated Arm Cortex-A9 MPCore processors running at 650MHz. The new Zybo Z7-10 and -20 dev boards are based on the Zynq Z-7010 and Z-7020 SoC respectively, and the processors now run at 667MHz. The Zybo Z7-10 sells for $199 (currently, you can get a voucher for the Xilinx SDSoC development environment for $10 more) and the Zybo Z7-20 board with triple the programmable logic resources sells for $299 (and currently includes the SDSoC voucher).
Digilent Zybo Z7-20 Dev Board based on Zynq Z-7020 SoC
In addition to the faster processors, there are several additional upgrades made to the Zybo Z7 versus the Zybo dev board. SDRAM capacity has increased from 512Mbytes on the original Zybo board to 1Gbyte on the Zybo Z7. The new boards now have two HDMI ports to support “bump-in-the-wire” HDMI applications. Both boards now also include a connector with a MIPI CSI-2 interface for video camera connections. You can plug a Raspberry Pi Camera Module directly into this connector and Digilent also plans to offer a camera module for this port.
Here’s a video explaining some of the highlights of the new Zybo Z7.
Note: For more information about the Zybo Z7 dev board, please contact Digilent directly.
XIMEA has announced an 8K version of its existing xiB series of PCIe embedded-vision cameras. The new camera, called the CB500, incorporates a CMOSIS CMV50000 sensor with 47.6Mpixel (7920x6004) resolution at 12bit conversion depth. The camera is available in either color or monochrome version and can stream 30fps at 8bits/pixel transport mode (22fps at 12bits/pixel transport mode). Both cameras employ a 20Gbps PCIe Gen2 x4 system interface.
Ximea 8K, 47.6Mpixel CB500 xiB embedded-vision camera with PCIe interface
Like many of its cameras, the XIMEA CM500 relies on the programmability of a Xilinx FPGA to accommodate the different interface needs and processing requirements of the sensors and interfaces in its cameras. In the case of the CM500, the FPGA is an Artix-7 A75T.
For information about the XIMEA CM500 8K camera, please contact XIMEA directly.
For more information about other XIMEA embedded-vision cameras based on Xilinx all Programmable devices, see:
Back in the early days of computing when only immense, big-iron computers roamed the earth, Stanley Frankel created the revolutionary LGP-30 desk computer. Back when the sale of one, two, or maybe three units per computer design was the norm, LibraScope built and shipped more than 500 LGP-30s from 1956 through the early 1960s. It proved to be a very durable design for the time. This tiny titan used only 113 vacuum tubes and 1450 newfangled germanium diodes (from the discard pile at Hughes Aircraft) to create a working computer. The LGP-30’s main memory and even its three 32-bit CPU registers were stored on its magnetic rotating-drum memory.
This ad for Stan Frankel’s LGP-30 personal computer appeared in the Proceedings of the IRE in April, 1959.
The LGP-30 was a significant milestone in computer history. It was the first computer to be used as a process-control machine due to its “low” $27,000 cost. John Kemeny and Thomas Kurtz at Dartmouth College used an LGP-30 during the early 1960s to develop several simplified programming languages designed for undergraduate study: DARSIMCO (Dartmouth Simplified Code), DART, ALGOL 30, SCALP (Self-Contained ALGOL Processor), and DOPE (Dartmouth Oversimplified Programming Experiment). They called the successor to these languages the Beginner’s All-purpose Symbolic Instruction Code (BASIC) but by the time they developed BASIC, they’d graduated to General Electric GE-225 and Datanet-30 computers.
Now, Jürgen Müller has developed a timing-faithful miniature replica of the LGP-30 called the LittleGP-30. It’s based on a Xilinx Spartan-6 LX9 FPGA, which recreates the LGP-30’s CPU and its rotating magnetic drum, reads the user controls, and drives the displays.
Jürgen Müller’s LittleGP-30 FPGa-based miniature replica of the 1950’s-era LGP-30 computer
You might well be expecting to see a big panel of blinking lights, as was common for computers of that era. However, the original LGP-30 used lighted pushbuttons to show the machine’s operational status and the internal machine state appeared on the front panel on an oscilloscope display. Müller has recreated the lighted pushbuttons using LED-backlit tactile switches and an LCD recreates the oscilloscope display. The 3-board LittleGP-30 uses a low-cost Numato MIMAS FPGA board based on a Spartan-6 LX9 FPGA. A custom control/display board with the LittleGP-30’s switches, LCD, a rotary encoder, and an HDMI port for displaying the entire contents of the machine’s emulated drum memory plugs into the Numato MIMAS board. A third circuit board on the top serves as a rather realistic reproduction of the LGP-30’s front panel—in miniature of course. Although it’s not currently a kit, Müller has posted a 42-page LittleGP-30 manual online.
Müller’s LittleGP-30 Web page also contains links to original LGP-30 paper-tape ASCII images, more than a dozen original software and hardware manuals, and a history of the LGP-30 computer that’s at the Computermuseum der Fakultät Informatik in Stuttgart. (The Computer History Museum in Mountain View also has an LGP-30 on display.)
Note: You can find out more about the history of Stan Frankel and the LGP-30 here.
Programmable logic is proving to be an excellent, flexible implementation medium for neural networks that gets faster and faster as you go from floating-point to fixed-point representation—making it ideal for embedded AI and machine-learning applications—and the latest proof point is a recently published paper written by Yufeng Hao and Steven Quigley in the Department of Electronic, Electrical and Systems Engineering at the University of Birmingham, UK. The paper is titled “The implementation of a Deep Recurrent Neural Network Language Model on a Xilinx FPGA” and it describes a successful implementation and training of a fixed-point Deep Recurrent Neural Network (DRNN) using the Python programming language; the Theano math library and framework for multi-dimensional arrays; the open-source, Python-based PYNQ development environment; the Digilent PYNQ-Z1 dev board; and the Xilinx Zynq Z-7020 SoC on the PYNQ-Z1 board. Using a Python DRNN hardware-acceleration overlay, the two-person team achieved 20GOPS of processing throughput for an NLP (natural language processing) application with this design and outperformed earlier FPGA-based implementation by factors ranging from 2.75x to 70.5x.
Most of the paper discusses NLP and the LM (language model), “which is involved in machine translation, voice search, speech tagging, and speech recognition.” The paper then discusses the implementation of a DRNN LM hardware accelerator using Vivado HLS and Verilog to synthesize a custom overlay for the PYNQ development environment. The resulting accelerator contains five Process Elements (PEs) capable of delivering 20 GOPS in this application. Here’s a block diagram of the design:
DRNN Accelerator Block Diagram
There are plenty of deep technical details embedded in this paper but this one sentence sums up the reason for this blog post about the paper: “More importantly, we showed that a software and hardware joint design and simulation process can be useful in the neural network field.” This statement is doubly true considering that the PYNQ-Z1 dev board sells for $229.
Just this month, IEEE Spectrum magazine ran an article written by Morgen E. Peck titled “Why the Biggest Bitcoin Mines Are in China.” The article primarily discusses Bitmain, a company that claims to have made 70% of the bitcoin mining rigs in the world. The company’s current top-of-the-line bitcoin-mining machine, the one that Bitmain says is the most powerful bitcoin miner in the world, is called the Antminer S9. Each Antminer S9 incorporates 189 of Bitmain’s 16nm ASIC, the BM1387. The Antminer S9 can execute 14 TeraHashes/sec in its fastest speed grade.
Bitmain’s Antminer S9, the world’s most powerful bitcoin miner
According to the IEEE Spectrum article, FPGAs were used to mine bitcoin until about 2013. After that, ASICs took over the heavy-duty task of running the bitcoin SHA-256 hashing algorithm as fast as possible. That’s because bitcoin mining is a race and the winner of the Bitcoin race is the fastest one to compute and register a hash that meets the criteria established for Bitcoin. The first to register that hash with the Bitcoin network owns that bitcoin, currently worth a little more than $6000 according to the exchange rate posted at the bottom of the Web page for the Antminer S9 mining machine.
So if the days of FPGA-based bitcoin mining are over, why cover Bitmain in an Xcell Daily blog? Because something needs to manage and direct the 189 ASICs in each Antminer S9 mining machine and that something is a Xilinx Zynq Z-7010 SoC according to Bitmain’s Antminer S9 Web page. Among the features that Bitmain liked about the Zynq SoC is that it “supports Gigabit Ethernet to ensure that mined blocks are submitted instantly” because finding the right hash is one thing, but being the first to register it is everything.
Xilinx has a terrific tool designed to get you from product definition to working hardware quickly. It’s called SDSoC. Digilent has a terrific dev board to get you up and running with the Zynq SoC quickly. It’s the low-cost Arty Z7. A new blog post by Digilent’s Alex Wong titled “Software Defined SoC on Arty Z7-20, Xilinx ZYNQ evaluation board” posted on RS Online’s DesignSpark site gives you a detailed, step-by-step tutorial on using SDSoC with the Digilent Arty S7. In particular, the focus here is on the ease of moving functions from software running on the Zynq SoC’s Arm Cortex-A9 processors to the Zynq SoC’s programmable hardware using Vivado HLS, which is embedded in SDSoC. That’s so that you can get the performance benefit of hardware-based task execution.
Digilent’s Arty Z7 dev board
Yesterday, DeePhi Tech announced several new deep-learning products at an event held in Beijing. All of the products are based on DeePhi’s hardware/software co-design technologies for neural network (NN) and AI development and use deep compression and Xilinx All Programmable technology as a foundation. Central to all of these products is DeePhi’s Deep Neural Network Development Kit (DNNDK), an integrated framework that permits NN development using popular tools and libraries such as Caffe, TensorFlow, and MXNet to develop and compile code for DeePhi’s DPUs (Deep Learning Processor Units). DeePhi has developed two FPGA-based DPUs: the Aristotle Architecture for convolutional neural networks (CNNs) and the Descartes Architecture for Recurrent Neural Networks (RNNs).
DeePhi’s DNNDK Design Flow
DeePhi’s Aristotle Architecture
DeePhi’s Descartes Architecture
DeePhi’s approach to NN development using Xilinx All Programmable technology uniquely targets the company’s carefully optimized, hand-coded DPUs instantiated in programmable logic. In the new book “FPGA Frontiers” published the Next Platform Press, DeePhi’s co-founder and CEO Song Yao describes using his company’s DPUs: “The algorithm designer doesn’t need to know anything about the underlying hardware. This generates instruction instead of RTL code, which leads to compilation in 60 seconds.” The benefits are rapid development and the ability to concentrate on NN code development rather than the mechanics of FPGA compilation, synthesis, and placement and routing.
Part of yesterday’s announcement included two PCIe boards oriented towards vision processing that implement DeePhi’s Aristotle Architecture DPU. One board, based on the Xilinx Zynq Z-7020 SoC, handles real-time CNN-based video analysis including facial detection for more than 30 faces simultaneously for 1080p, 18fps video using only 2 to 4 watts. The second board, based on a Xilinx Zynq UltraScale+ ZU9 MPSoC, supports simultaneous, real-time video analysis for 16 channels of 1080p, 18fps video and draws only 30 to 60 watts.
DeePhi PCIe NN board based on a Xilinx Zynq Z-7020 SoC
DeePhi PCIe NN board based on a Xilinx Zynq UltraScale+ ZU9 MPSoC
For more information about these products, please contact DeePhi Tech directly.
The $89 Avnet MiniZed board is such a cool tool for fast-paced embedded design with its on-board Zynq Z-7007S SoC, WiFi, Bluetooth, Arduino shield header, and USB 2.0 host interface. Now, you can get a no-cost head start using this board through a 1-hour Webinar scheduled for November 15 titled “$89 MiniZed: Up Your Game in Embedded Design.”
Avnet’s $89 MiniZed Dev Board Block Diagram
For more information about the Avnet MiniZed board, see “Avnet’s $89 MiniZed dev board based on Zynq Z-7000S SoC includes WiFi, Bluetooth, Arduino—and SDSoC!”