05-26-2017 08:25 AM
I want to implement an UART block in Kintex7 KC705 Evaluation board, I couldn't get it working.
I did the same thing on nexys4 DDR and nexys4 Video, it has worked fine. the nexys4 boards have only mini usb connector,
KC705 has on uart connector and mini-Usb, I join here the schematic, can anybody tell-me what's wrong, or what to do ? which cable and connector I have to use, or any jumper positionning ??,
Thanks in advance
05-26-2017 08:52 AM
Yes, the pin locations are correct (the names on the board are with respect to the USB to UART converter).
The correct connector is the one marked UART.
There are no jumpers required for the UART to work.
Of course, you need to have the proper USB to UART driver (Virtual COM port) installed on the computer connected to the USB port...
Other than that, you need to debug the system. One thing that you can do to establish that your board and PC setup are correct is to create a load that connects the usb_tx to the usb_rt (essentially have the FPGA act as a loopback). If your board and PC setup are correct then you will see the characters echoed on a terminal program on your PC (make sure you have local character echo turned off in the terminal program).
05-26-2017 10:41 AM
I did that (Scilab CP210 USB bridge installed), I try to converse throug a python script, as I said the bench worked with nexys4DDR, I join schematic to explain this. (Baudrate in FPGA and Python are correctly programmed), this flow (Python to FPGA worked with NEXYS4 DDR), please look to this schematic attached here
05-26-2017 01:10 PM
The connections look right - you will have to debug this yourself.
There are lots of things in this chain (Python, Virtual COM port, USB cable, USB-UART converter, FPGA) there and back. I would suggest simplifying as much as you can.
Forget the Python for now and start with a terminal emulator (putty, teraterm, etc...). As I mentioned before, create an FPGA load that has only the loopback. This is the "minimim" amount of stuff needed to get communication going. If you get this working, then you can add back the rest of your stuff (the UART RX and TX in the FPGA, the Python...)
05-27-2017 05:21 AM
Now I'm sure that the problem is between Python script and the Scilab CP2103 driver. I did followings
1) I made the UART in FPGA, replies to any character received (by fixed ascii value)
2) I Run Tera-term with right baudrate and enabling local echo ( setup terminal, and setup serial port)
3) each time I type a character I received the right answer from my UART
I have to find why my serial function of python 3.4.1 cannot communicate with the virtual COM (Scilab CP2103 driver)