02-23-2015 12:00 PM
I am wondering if the community of VC709 users can help me out? If you have VC709 evaluation board, does your BPI flash work after you have booted from flash?
After booting from flash into a simple C program or into u-boot/Linux then I believe that you should be able to access the flash and read its contents. (maybe I am asking too much?) Unfortunately with the three VC709 boards that I have, the flash is completely locked up after I boot from it and there is nothing that I have figured out to get it back into read array mode.
I have read a number of the technical briefs about the BPI and verified and re-verified that my board is in good working order and that all the pins/jumpers are configured appropriately. Also, I have explored a number of drivers and tested their flash access routines and debugged how they execute the flash commands to restore the flash to read array mode, but nothing seems to clear the issue after I boot from the BPI flash. It seems to be completely locked up.
This issue is a show stopper for me, because I would like to store my bitstream combined with the first boot program in the flash, then boot up and have it load and jump to u-boot. This is all well-documented in the Xilinx reference designs, but it doesn't work on any of my three VC709 boads.
Strangely enough, if I place the u-boot into flash and then load the bitstream program over JTAG (instead of storing it in flash), then everything works fine. This is not a production solution, but it does confirm that all the software is intact and capable of booting the system. It is just that when you store the bitstream to flash, then power-on and boot from the BPI flash that it becomes locked up.
You can demonstrate the same problem with the VC709 BIST code provided by Xilinx. Here are the steps to re-create:
My management is ready to send all three VC709 evaluation boards back. I am trying to figure out how to work-around this issue or trying to learn something that maybe I have done wrong. If there is somebody from Xilinx on this thread, can you confirm if I am doing something wrong? Do you see this issue with BIST and a VC709 board that you have in your lab? Any help is appreciated...
05-19-2015 03:10 PM
I recently sat down with another engineer in my office and figured this one out.
This issue is caused by the FLASH being used in synchronous mode versus asynchronous mode. If you change the following settings in your bitstream generation, then you will be able to access the flash after loading the bitstream from it.
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [get_designs impl_1]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE DISABLE [get_designs impl_1]
The reason that the BIST test for FLASH fails is because it is trying to acces the flash without a clock and yet the flash is in synchronous mode and requires a clock. There doesn't appear to be a way to switch these eval boards back to asynchronous mode after booting in synchronous mode. Thus, the two settings above setup the bitstream to be booted in asynchronous mode -- effectively punting on synchronous mode.
Once I did this, then I can access the flash after I have booted from it. Now I can boot the bitstream, run fs-boot, load u-boot and run the linux kernel all from the same flash.
Strange that when I originally presented this issue to Xilinx in a Webcase that they decided to RMA my board?
If you download and install the various releases of the Xilinx BIST code, you can see that they changed the BIST over from asynchronous mode access of the flash to synchronous mode. Synchronous mode has the promise to be faster, but after booting from flash with these eval boards you are stuck.
2014-1 bist app from Xilinx - Boots in asynchronous mode, BIST flash test passes
2014-2 bist app from Xilinx - Boots in asynchronous mode, BIST flash test passes
2014-3 bist app from Xilinx - Boots in synchronous mode, BIST flash test fails
2014-4 bist app from Xilinx - Boots in synchronous mode, BIST flash test fails
02-23-2015 07:52 PM
what is the mode pins set in SW11 when you do the power cycle to run the BIST from bpi flash.
it must "010"
check the user guide table A-2
02-23-2015 09:44 PM
Please check the AR - http://www.xilinx.com/support/answers/54355.html and try to make sure all the board led and jumper settings are as per this and then run the BIST. Also check the section 6 for BPI device debugging.
02-24-2015 09:32 AM
> My management is ready to send all three VC709 evaluation boards back.
This isn't a problem with the VCU709 board, it is a problem with your design. The likely problem is that the configuration from the BPI flash has left in a mode that was not expected by the processor code and the flash device needs to be reset.
02-24-2015 09:59 AM
Yes, the mode pins are set to 010. I have gone through all the docs trying to figure out if I have the wrong settings. It is pretty straight forward, just doesn't work.
02-24-2015 10:05 AM
I agree that the flash device just needs to be reset and put into readarray mode, but when would boot up any bitstream from the flash, the flash is not resettable as far as I can tell. (It is locked up) I have downloaded and installed the specific driver for this flash from Micron. Wrapping that driver with a simple C program yields the same results: If you program the bitstream (MSC) file to the flash and then reset the board micron driver is useless in resetting the flash, reading the device ID, or placing the device in read array mode.
I would like to figure a way around this. It is a pain to not be able to read the flash after booting from it.
02-24-2015 10:09 AM
I thought at first that it was my design that was the problem, but then the Xilinx provided BIST design shows the same issue. This leads me to believe that it is more of a board problem then a code or design problem. When I load the Xilinx provided BIST code, I don't compile it even but rather just use the MCS file provided in the zip file.
Do you see this on your VC709 boards?
02-24-2015 04:28 PM
Can you point me towards a Xilinx reference design that demonstrates that the flash is readable after you boot from it? I am happy to concede that my design must be wrong somehow, but it is difficult to believe that my design is wrong when I am just using a Xilinx reference design to demonstrate the problem?
03-03-2015 09:39 PM
You can check and try using the mcs file from the multiboot design from this link - link. Check for XTP236.
Check if the mcs in this should help program the FPGA from the BPI after programming.
03-22-2015 12:36 PM
I too am experiencing this exact issue on the VC707. If I program the FPGA via JTAG, I can read from the Flash fine. If the FPGA is programmed from the Flash, Xflash_Initialize() fails and I can't interact with the flash.
This person also seems to be having the same problem: http://forums.xilinx.com/t5/7-Series-FPGAs/FSBL-can-t-read-from-BPI-x16-flash-for-vc709/td-p/559297
Can a Xilinx engineer please look at this and at least get the BIST demonstration working?
If I get a chance, I'm going to Chipscope (or whatever it's not called in Vivado) the flash lines and see if there's any difference in JTAG vs Flash programming.