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Rmccarty
Adventurer
Adventurer
505 Views
Registered: ‎09-05-2020

On demand Vivado course #3 lab confusion

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The lab for Sampling and Capturing in Multiple Clock Domains ( Dgb_MultipleClkDomains ) does not work. It is claimed that the lab targets the zcu104,  but I get multiple critical synthesis and terminal implementation errors that appear to be caused by object instantiations ( IDDRE & ODDRE ) and xdc files ( wave_gen_timing.xdc ) targeting the ultrascale ( not + ) kcu105.

No way I'm going to blindly try to download the provided "solution" bit file into my zcu104  when it appears that nobody ever tried syth & implementation with the provided project.

Can I please have a working, tested project for this lab targeting the zcu104?

doesn't seem like too much too ask as I paid for the course and have the 'recommended' board and Vivado 202.1 already installed.

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Rmccarty
Adventurer
Adventurer
89 Views
Registered: ‎09-05-2020

Update works great!

 

View solution in original post

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8 Replies
omkarviv
Xilinx Employee
Xilinx Employee
434 Views
Registered: ‎09-21-2018

Hello User,

Thanks for contacting us. We will look into this and get back to you as soon as possible. Sorry for the inconvenience.

Thanks and Regards,

Omkar Vivek Bhat 

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Rmccarty
Adventurer
Adventurer
388 Views
Registered: ‎09-05-2020

Hi Omkar,

Thank you. Any update on this?

I am all finished with the 3rd Viviado course with the exception of this lab. I spent some time trying to convert the lab to the ZCU104 myself, but encountered too many things I don't understand relating to the XDC files.

Regards, Rich

Rmccarty
Adventurer
Adventurer
335 Views
Registered: ‎09-05-2020

Hello @omkarviv 

Any news about this lab?

Please note that I am not trying to be pedantic. I understand that the lab instructions say that one can skip the synthesis and implementation steps and load the provided bit stream in order to save time, but I really want to analyze and inspect the design using the various reports provided by syth and implementation. I also understand that I could simply click the lab completed checkbox and move on, but I am a relative beginner to FPGA design and being able to inspect the design will help alot in trying to understand how the timing constraints work with respect to how the multicyle and false path and async clock groups interact with the logic.

 

Regards, Rich 

Rmccarty
Adventurer
Adventurer
305 Views
Registered: ‎09-05-2020

Great, I have apparently been ghosted by a huge multinational corporation by simply asking that they fix an obviously incorrect lab in a course that I payed for. I guess I incorrectly assumed that the coursework provided by Xilinx would have been tested before it was released. 

I cannot finish the course until this lab actually works. No amount of crowd sourcing will fix Xilinx's internal sloppiness.

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omkarviv
Xilinx Employee
Xilinx Employee
253 Views
Registered: ‎09-21-2018

Hi Rich,

Extremely sorry for your inconvenience . I am myself having some trouble, but I working on it. Give me just one more day, I will fix this issue. 

Thanks and Regards,

Omkar Vivek Bhat 

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Rmccarty
Adventurer
Adventurer
211 Views
Registered: ‎09-05-2020

Great!

Your effort will not be wasted, I really want to spend the time to understand this design. Sorry for being a PIA but I'm still very suprised that nobody else noticed and cared enough to complain.

Are there any plans to migrate all the Vivado labs to the ZCU104?

Regards, Rich

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omkarviv
Xilinx Employee
Xilinx Employee
187 Views
Registered: ‎09-21-2018

Hi Rich,

First of all thanks for your patience.  I am suppose to be help you out for this question, but I was not well and out of office but now I have started debugging it, facing some issues but I will give solution very soon.

About ZCU104 migration plan, We do have all the download labs targeting to ZCU104, but apart from them all other software based lab will be continuing to target UltraScale KCU105 board. In future release we are planning to add versal VCK190 based software lab in to the course.

Thanks and Regards,

Omkar Vivek Bhat

 

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Rmccarty
Adventurer
Adventurer
90 Views
Registered: ‎09-05-2020

Update works great!

 

View solution in original post

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