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Newbie
Newbie
4,892 Views
Registered: ‎03-30-2011

50Mhz Clock Dividing to 30Mhz..

I'm not really sure how to go about doing this...

 

My application:

 

I have 3 ADCs sampling at 10 Mhz (100 ns) Simultaneously

 

I have a multiplexer that grabs the data off each ADC, Feeds it into a buffer which gets shoved into RAM via Burst Write mode.

 

My nexys 2 board has a 50 Mhz (20 ns, samples 3 ADCs 5 times..) crystal oscillator. If I use that, I end up grabbing the Data from ADC 1 and ADC 2 twice. I do not want to do that.

 

So I did the math out, If I want to grab the data off the 3ADCs within the sample time I would need a clock speed of 30Mhz (100 ns/ 33.333 ns ~ 3 )

 

so Basically I need to go from a 50Mhz to a 30 Mhz clock.. so basically the clock needs to say High for 16.66ns and low for 16.66 ns. I can't seem to do it using a conventional method of using a counter.. any thoughts?

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Instructor
Instructor
4,890 Views
Registered: ‎07-21-2009

Re: 50Mhz Clock Dividing to 30Mhz..

You don't need a 30MHz clock to read or sample periodically.  As long as the ADC interfaces will run at 50MHz, why not run the interfaces at 50MHz?

My nexys 2 board has a 50 Mhz (20 ns, samples 3 ADCs 5 times..) crystal oscillator. If I use that, I end up grabbing the Data from ADC 1 and ADC 2 twice.

I don't think a clock frequency change is likely to affect this problem.  It will only make the problem "run" faster or slower.

 

-- Bob Elkind

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Newbie
Newbie
4,869 Views
Registered: ‎03-30-2011

Re: 50Mhz Clock Dividing to 30Mhz..

I'm using external ADCs that run at max of 10Mhz.

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Instructor
Instructor
4,866 Views
Registered: ‎07-21-2009

Re: 50Mhz Clock Dividing to 30Mhz..

I'm using external ADCs that run at max of 10Mhz.

How can we help you?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
4,843 Views
Registered: ‎02-25-2008

Re: 50Mhz Clock Dividing to 30Mhz..

 


@tehpyrate wrote:

I'm not really sure how to go about doing this...

 

My application:

 

I have 3 ADCs sampling at 10 Mhz (100 ns) Simultaneously

 

I have a multiplexer that grabs the data off each ADC, Feeds it into a buffer which gets shoved into RAM via Burst Write mode.

 

My nexys 2 board has a 50 Mhz (20 ns, samples 3 ADCs 5 times..) crystal oscillator. If I use that, I end up grabbing the Data from ADC 1 and ADC 2 twice. I do not want to do that.

 

So I did the math out, If I want to grab the data off the 3ADCs within the sample time I would need a clock speed of 30Mhz (100 ns/ 33.333 ns ~ 3 )

 

so Basically I need to go from a 50Mhz to a 30 Mhz clock.. so basically the clock needs to say High for 16.66ns and low for 16.66 ns. I can't seem to do it using a conventional method of using a counter.. any thoughts?


 

Sounds like a problem for a simple state machine.

 

Or you could replace the 50 MHz oscillator with a 30 MHz oscillator and get on with your life.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
4,807 Views
Registered: ‎11-26-2008

Re: 50Mhz Clock Dividing to 30Mhz..

 


@tehpyrate wrote:

...

so Basically I need to go from a 50Mhz to a 30 Mhz clock.. so basically the clock needs to say High for 16.66ns and low for 16.66 ns. I can't seem to do it using a conventional method of using a counter.. any thoughts?


 

If by "conventional" method you mean using a counter to generate a new clock, you should probably have a look at using clock enables (or a DCM) instead. Gated / derived clocks can introduce subtle timing problems, especially when used with multiple clock domains. Also, if you make several of these, you'll quickly use up all your clock lines in the FPGA. Clock enables have neither of these problems, and also allows you much better control of the timing granularity...

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