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Visitor
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Registered: ‎02-10-2017

7 Series FPGA transceiver wizard example project issues

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Hi all, I am using a ZC706 evaluation board and Vivado 2015.2. I am fairly inexperienced in FPGA design but here it goes.  
I am currently trying to get the 7 series fpga transceiver wizard example project up and running but I am having some problems when I implement it in hardware and check the output signals with ILAs. 

First of all I am doing the transceiver wizard setup with 6G settings (148.5 MHz reference clock, 5.94 Gbps line rate):

setup2.PNG

I have already made sure on a separate project with IBERT that I have an existing link at the X0Y0 transceiver (using a loop-back connector and an external 148.5 MHz clock from an FMC board). 

Now, the issue is the following, the tx data generated from the frame generator does not match with the rx data: 

Output TX signal (gt0_txdata_in[39:0]):
tx.PNG
RX signal (gt0_rxdata_i[39:0]):
rx.PNG

I assume that I should be seeing the same exact signal for RX as in TX, so I must be doing something wrong. I haven't changed anything in the example design except changing the DRP_CLK in the constraints file:

set_property IOSTANDARD LVDS [get_ports DRP_CLK_IN_N]
set_property PACKAGE_PIN H9 [get_ports DRP_CLK_IN_P]
set_property PACKAGE_PIN G9 [get_ports DRP_CLK_IN_N]
set_property IOSTANDARD LVDS [get_ports DRP_CLK_IN_P]

Basically, I am setting the DRP_CLK to SYS_CLK of this board (which is 200 MHz). I do not know if this is wrong, in the transceiver wizards the DRP clock option is greyed out so I have no option but to use it:

settings.PNG
And it is limited to 0 - 175.01 MHz according to the wizard. I am giving it 200 MHz, but I read in some other forum posts that this DRP clock is just the system clock so maybe it is not an issue? Would appreciate any kind of help with this. 

Also, I have a side question: can this generated frame be output to a display and show an image? Or is it just random data? 

 

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Xilinx Employee
Xilinx Employee
9,716 Views
Registered: ‎02-14-2014

Re: 7 Series FPGA transceiver wizard example project issues

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Hello @jonathanfei,

 

I checked the customization file which you have sent and it seems you are not using either comma alignment or RXSLIDE port to align the data and hence misalignment is being observed every time you reprogram the device.This is because if you do not enable either of the alignment method, there is no way for receiver to figure out correct start of frame. I have attached snapshot of your customization which shows the same. 

 

So the correction would be using either of these method to get data correctly aligned. Correct approach would be referring below application note (which is designed and verified with KC705 device) and building your design for ZC706 as per guidelines mentioned here. 

https://www.xilinx.com/support/documentation/application_notes/xapp1200-k7-xcvr-wiz-example-design.pdf

Regards,
Ashish
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transceiver.PNG
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Moderator
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Registered: ‎02-16-2010

Re: 7 Series FPGA transceiver wizard example project issues

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The limit on DRP/system clock frequency is based on the GT spec for DRP clock.

I find the encoding is set to "None". Are you enabling "comma alignment" in the design?
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Xilinx Employee
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Registered: ‎02-14-2014

Re: 7 Series FPGA transceiver wizard example project issues

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Hello @jonathanfei,

 

Can you please share IP customization file (.xci) to know details regarding transceiver blocks being used in your design?

Regards,
Ashish
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Visitor
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Registered: ‎02-10-2017

Re: 7 Series FPGA transceiver wizard example project issues

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Hi all, thanks for your replies. 
I am attaching the .xci file for the IP. 
Because I wish to implement 6G-SDI I have set the line encoding to none. 

By the way, since last time I have made some progress. This is what I can see now on the ILAs: 

TX: 
txv2.PNG

For RX, I can now see a similar pattern but it is still strange. Whenever I press on Run Trigger I get a somewhat different result (I will attach 3 examples):

rxdata.PNG


rxdata2.PNG

rxdata3.PNG

In all of the above examples I am using a loop back connector on my transceiver. If I disconnect the loopback connector I see the following for RX: 

rxdata4.PNG
Does this indicate that at least the transceiver is working as intended?

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Visitor
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Registered: ‎02-10-2017

Re: 7 Series FPGA transceiver wizard example project issues

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@venkata @ashishd I forgot to mention, I am not enabling comma alignment as you can see from the .xci file

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: 7 Series FPGA transceiver wizard example project issues

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Hello @jonathanfei,

 

I can try implementing transceiver wizard example design on ZC706 board using the customization (.xci) which you have shared.and share the outcome. But meanwhile, if the purpose is to validate the transceiver link, then your best bet should be using IBERT example design and observe the link status. Below document can be helpful for the same -

https://www.xilinx.com/support/documentation/boards_and_kits/zc706/2013_2/zc706-ibert-xtp243-2013.2-c.pdf

Regards,
Ashish
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Visitor
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Re: 7 Series FPGA transceiver wizard example project issues

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Hi @ashishd, I already verified the transceiver link with IBERT. It works fine, the main issue is the receiver data I am seeing which is not completely the same as the TX data.

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Xilinx Employee
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Registered: ‎02-14-2014

Re: 7 Series FPGA transceiver wizard example project issues

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Hello @jonathanfei,

 

I checked the customization file which you have sent and it seems you are not using either comma alignment or RXSLIDE port to align the data and hence misalignment is being observed every time you reprogram the device.This is because if you do not enable either of the alignment method, there is no way for receiver to figure out correct start of frame. I have attached snapshot of your customization which shows the same. 

 

So the correction would be using either of these method to get data correctly aligned. Correct approach would be referring below application note (which is designed and verified with KC705 device) and building your design for ZC706 as per guidelines mentioned here. 

https://www.xilinx.com/support/documentation/application_notes/xapp1200-k7-xcvr-wiz-example-design.pdf

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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transceiver.PNG