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Registered: ‎11-19-2018

7 Series Memory Mapped PCIe Simulation not working


working on a  project using xilinx artix 100t Devices with Memory Mapped PCIe Single lane GEN1 .

Generated Example project for simulation , got few errors

i)  Got Error  ->  BRAM version mismatch .

    Using TCL Command  able to put back the BRAM 4.1 version on the Project list. 

ii)  While running simulation got  error  viz   axi_rid  ports  missing ect  

    Disbaled the some of the ports of BRAM so that simulation moves on  


Attached is the Snap shots of errors while creating a example from PCIe Core , so we can integrate the same to the custom design for furture simulation.  


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Xilinx Employee
Xilinx Employee
Registered: ‎07-26-2012

Re: 7 Series Memory Mapped PCIe Simulation not working

This issue has been reported. It was fixed in Vivado 2019.1. Can you try Vivado 20191.?

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