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Registered: ‎05-09-2019

AC701 MIG DDR3 Design example doesn't meet timing

Attnetion Xilinx Forum:

I have an AC701 board and followed xtp225 April 15 AC701 MIG Design Creation document. I tried to generate a bit stream but failed to meet timing. I went through the steps several times, used several versions of Vivado, and failed to meet timing. Could anyone give me some guidance?

Thanks,
Ken Farley

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