cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
mdr
Visitor
Visitor
10,570 Views
Registered: ‎06-06-2013

AC701 Routing Question

Jump to solution

We've got an AC701 board to which we've attached an XM105 debug card on the mezzanine connector.

 

UG952 shows the pin names for connections to/from the debug card, but there are several that fail on implementation. Vivado tells me that they are invalid route names. The failing pins are listed below, with the 'Schematic Net Name' found in UG952:

 

U4.27      "FMC1_HPC_GBTCLK1_M2C_P"
U4.25      "FMC1_HPC_GBTCLK1_M2C_N"
U52.19   "FMC1_HPC_IIC_SCL"
U52.20   "FMC1_HPC_IIC_SDA"
U3.27     "FMC1_HPC_GBTCLK0_M2C_P"
U3.25     "FMC1_HPC_GBTCLK0_M2C_N"
U19.13   "FMC1_HPC_TCK_BUF"
U19.17   "FMC1_TDI_BUF"
U19.2     "FMC1_TDO_FPGA_TDI"
U19.15   "FMC1_HPC_TMS_BUF"


How do I create these constraints in XCD form, when it looks like U3, U4, U5, and U19 are all a single pin? Are the extra numbers after the decimal referencing a bit in an array or something? What do these mean?

 

 

0 Kudos
1 Solution

Accepted Solutions
athandr
Xilinx Employee
Xilinx Employee
18,740 Views
Registered: ‎07-31-2012

Hi,

 

These are not actualy location on the FPGA. These indicate a pin in that specific module on the board. Eg U4.27 and U4.25 means, the pins 27 and 25 of the U4 mux input. Ideally, the pin locations for these modules should be given as AA13 and AB13. Refer Table 1-11 of UG952. This is a clock mux which select one among the 4 input clocks and in this case it is the FMC clocks. 

 

Similartly check for the other pins to get a clearer picture on what the final FPGA pin names are.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

3 Replies
mcgett
Xilinx Employee
Xilinx Employee
10,562 Views
Registered: ‎01-03-2008

When you have a problem you need need to post the entire error message that is reported by the tools as it isn't clear what the problem is.

 

Some of these are dedicated pins and not user I/O (*TMS*, *TDO*, *TDI*, *TCK*).   Some are special purpose and not user I/O (*GBTCLK*).  The last two (IIC_SCL, IIC_SDA) should be connected to user I/O, so it is unclear what the problem is without the error message.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
0 Kudos
athandr
Xilinx Employee
Xilinx Employee
18,741 Views
Registered: ‎07-31-2012

Hi,

 

These are not actualy location on the FPGA. These indicate a pin in that specific module on the board. Eg U4.27 and U4.25 means, the pins 27 and 25 of the U4 mux input. Ideally, the pin locations for these modules should be given as AA13 and AB13. Refer Table 1-11 of UG952. This is a clock mux which select one among the 4 input clocks and in this case it is the FMC clocks. 

 

Similartly check for the other pins to get a clearer picture on what the final FPGA pin names are.

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

View solution in original post

mdr
Visitor
Visitor
10,524 Views
Registered: ‎06-06-2013

That was exactly what I was looking for. Thanks!

0 Kudos