ADCs connecting to FMC connector with serial LVDS: preferred order of connections?

[larrylucas]

I am designing a FMC daughtercard that uses a quad ADC (Linear 9012) with serial LVDS outputs. Each of the four ADCs has two LVDS pairs (DA+, DA-, DB+, DB-) as two bits are sent at a time to lower the clock rate. In addition, clock output and frame output are also on LVDS pairs. So there are a total of 10 LVDS pairs (20 traces) to the low-pin-count FMC connector. Each LVDS pair goes to a LAxx pair. Most of the 32 LAxx pairs are unused.

For the greatest ease of connection, the LAxx pairs used would not be sequential. How much difference does that make? One can always rearrange signals inside of the FPGA, but that does use some of the resources to do. In particular, for the two bits from the same ADC, is it advantageous to at least have those two LAxx pairs sequential? Or is it better to look at the pin connections on the FPGA (Zynq 700) and have the two pairs of pins adjacent there? Or does it not matter for so few connections?

[umamahe]

Are you using any Xilinx supplied  board (Ex: ZC702 / ZC706)? Please clarify?

(It seems you are using own customer board. In that case I will move this post to correct forum board.)

[john.potter@redsensors.co.uk]

Can you confirm which forum you moved the query too?

[embedded]

@larrylucas,

It wouldn't need any resource inside the FPGA!. But, be careful of your bit rates and the fact that IOs of various Banks have different delays to the fabric!. If you are going to route lines to different banks you may need to trim their delays inside FPGA even if you have routed the same length outside the FPGA!. I mean for high bit rates you may need to use an IDELAY to compensate such delays. Otherwise, you don't need to be worried about it.

If you want to know when you have to be careful, this is completely according to your ADC output rate and the FPGA!. You have not mentioned these data.

Hope this would be helpful,

Hossein