09-23-2016 03:10 AM
I have a question regarding the AXI Interconnect and the AXI GPIO IP. First a few details regarding the Project that I am working on.
Right now I am using the ZYNQ 7020 rev C1 with PetaLinux and the build in UIO framework to access the registers of a memory-mapped device implemented in the zynq’s programmable logic fabric. The main goal is to send a command string from my PC to a custom zynq board via Ethernet and set the register values of the device based on the command string. So far so good.
I set up PetaLinux and wrote a simple C application and everything works fine, but it is too slow. Latency is really important for me.
For testing purposes I used the AXI Interconnect and the AXI GPIO to toggle a pin as fast as possible. I wrote a simple baremetal application with Xilinx SDK to make sure it had nothing to do with Linux. In the vivado project I set the FCLK_CLK0 to 50, 100 and 250 MHz and the frequency at which I am able to toggle the pin was 1.1 MHz, 2.2 MHz and 3.8 MHz.
My Question is how I can achieve higher frequencies (10MHz) using the AXI GPIO. Is it possible or am i doing something wrong?
Hope you guys can help me.
09-23-2016 04:48 AM
I'm not sure that toggling a pin over AXI via the PS is really a good idea.
If you need regular toggling (eg. PWM), use the AXI Timer IP (or write your own). Then you send it the relevant settings (speed non-critical) and let it generate cycle-accurate timing by itself. If the toggling is irregular (eg. bitbanging some odd communications protocol), I'd either write a custom bit of HDL code or stick a Microblaze (or Microblaze MCS) in there. Either would be more suitable for the task than the Zynq CPU.
09-23-2016 02:32 PM
09-25-2016 11:00 PM
Thanks for the reply,
To toggle the pins was just for testing purposes. In the end I’ll just have a few registers in the PL, which values I need to write and read relatively quickly. It won’t be streaming, but single random access of the registers.
You said I might need to move the control logic to PL. Which control logic do you mean? Do you know the maximum speed that could be achieved using axi gpio to write and read the registers?
09-26-2016 07:06 AM - edited 09-26-2016 12:17 PM
>> Which control logic do you mean?
The logic which will do "values I need to write and read relatively quickly" as you mention in your post. Between the reads and writes there has to be some logic which decides what to write based on what it reads. That piece of code should move to PL if it has to work "relatively quickly"
In my experience, each GP access can be done in 150-200 ns.
06-19-2017 12:15 PM
I was also quite disappointed with ~2 MHz maximum toggling rate. However, it can be done about 5 times faster if instead of using AXI toggle them on MIO with <xgpiops.c>.