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fpegios
Visitor
Visitor
11,080 Views
Registered: ‎10-14-2015

Adjust KC705 clock input to 100Mhz

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Hello,

 

I am using Kintex7 board and I would like to change the clock input to 100Mhz.

As I have read from the KC705 manual, it says that:

 

"The KC705 board has a 2.5V LVDS differential 200 MHz oscillator (U6) soldered onto theback side of the board and wired to an FPGA MRCC clock input on bank 33. This 200 MHz signal pair is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins AD12 and AD11 respectively."

 

So how can i have 100Mhz clock input?

 

Thanks in advance!

-Fotis

 

 

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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gszakacs
Instructor
Instructor
19,662 Views
Registered: ‎08-14-2007

I assume these two commented-out lines were in the original XDC that came with the KC705?

 

#create_clock -period 5.000 -name tc_clk_p -waveform {0.000 2.500} [get_ports {clk_p}]
#create_clock -period 5.000 -name tc_clk_n -waveform {2.500 5.000} [get_ports {clk_n}]

 

That would indicate that:

 

A) the clock input is differential and requires an IBUFGDS instantiated in your code.

B) the clock frequency is 200 MHz.

 

So you need to add some code to create a 100 MHz clock from this 200 MHz differential clock input.  You can't change the input frequency by adjusting the XDC file.  The XDC just tells the tools what to expect on the inputs.  Changing what the tools expect doesn't change what they FPGA actually gets.  A 200 MHz oscillator won't suddenly oscillate at 100 MHz because you made an edit to the XDC file.

-- Gabor

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8 Replies
austin
Scholar
Scholar
11,077 Views
Registered: ‎02-27-2008

f,

 

Use thew mixed-mode clock manager (MMCM) to convert the 200 MHz to `100 MHz (or any number of frequencies that you may wish for).

 

https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CBwQFjAAahUKEwi5ndeMwdTIAhVSLYgKHVIMCO4&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fuser_guides%2Fug472_7Series_Clocking.pdf&usg=AFQjCNEytziwgBm...

Austin Lesea
Principal Engineer
Xilinx San Jose
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fpegios
Visitor
Visitor
11,071 Views
Registered: ‎10-14-2015
Hi,

Is it the same with PLLE2_BASE?
--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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gszakacs
Instructor
Instructor
11,059 Views
Registered: ‎08-14-2007

PLLE2_BASE is a subset of the MMCM, but it is good enough to do what you need.  The easiest way to use either PLL or MMCM is via the clocking wizard.

-- Gabor
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fpegios
Visitor
Visitor
11,049 Views
Registered: ‎10-14-2015

Hello,

 

I have these files. Is signal "clk" 100 Mhz? O r I have to use also create_clock constraint?

 

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
0 Kudos
gszakacs
Instructor
Instructor
19,663 Views
Registered: ‎08-14-2007

I assume these two commented-out lines were in the original XDC that came with the KC705?

 

#create_clock -period 5.000 -name tc_clk_p -waveform {0.000 2.500} [get_ports {clk_p}]
#create_clock -period 5.000 -name tc_clk_n -waveform {2.500 5.000} [get_ports {clk_n}]

 

That would indicate that:

 

A) the clock input is differential and requires an IBUFGDS instantiated in your code.

B) the clock frequency is 200 MHz.

 

So you need to add some code to create a 100 MHz clock from this 200 MHz differential clock input.  You can't change the input frequency by adjusting the XDC file.  The XDC just tells the tools what to expect on the inputs.  Changing what the tools expect doesn't change what they FPGA actually gets.  A 200 MHz oscillator won't suddenly oscillate at 100 MHz because you made an edit to the XDC file.

-- Gabor

View solution in original post

fpegios
Visitor
Visitor
11,035 Views
Registered: ‎10-14-2015
Ok, but with the PLLE2_BASE i used i divide the clock input from 200Mhz to 100Mhz.
--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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gszakacs
Instructor
Instructor
11,026 Views
Registered: ‎08-14-2007

@fpegios wrote:
Ok, but with the PLLE2_BASE i used i divide the clock input from 200Mhz to 100Mhz.

That's right.  Still the clock inputs clk_p/clk_n are running at 200 MHz, so you only need to use the original create_clock with period 5 ns in your XDC.  Vivado will understand that this gets divided by 2 as it goes through the PLL, and it will generate a "derived" constraint for the 100 MHz clock that goes to your logic.

-- Gabor
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fpegios
Visitor
Visitor
11,018 Views
Registered: ‎10-14-2015
Ok, I am happy to hear that I have solved my problem!

Thanks for the help!
--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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