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Visitor
Visitor
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Registered: ‎07-24-2013

Aurora Loopback on ZC706 board

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Hello,

 

I am relatively new to Aurora cores, and IP integrator.

 

I have been trying to replicate the "xapp1192" on ZC706 board. I could get the second example to work smoothly  (internal loopback -- PCS and PMA) but for the first example, I had to modify the design because of the lack of two boards. Following is my scenario:

1) ZC706 board

2) FMC board (HTG-FMC-CX4-SATA-SMA)

 

I plan to complete the external loopback using two different clocks (one from SMA and one from FMC-LPC). So, I am using IP integrator to customize and instantiate two different Aurora (64B/66B) cores. While customizing the cores, I am a little puzzled I plan to use the GTX_BANK_111 which enables both FMC_LPC and SMA clocks as the MGT reference clocks.

 

How do I address the rest of the clock signals of the core (like sync clk, usr clk...)?

 

Thanks in advance.

S

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: Aurora Loopback on ZC706 board

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Hi,

drp_clk_in can be common for both master and slave and it can come from external source.

Regards,
Krishna
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Moderator
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Registered: ‎02-16-2010

Re: Aurora Loopback on ZC706 board

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I believe you are trying to create a design with 2X1 lane design. If the core configuration is same with both single lane design, you should create

one of the core with "Shared logic in core" -- master
second core with "Shared log in example design" -- Slave

the clocks -- sync_clk, usr_clk will be generated by master and can be connected to slave.
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Visitor
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Registered: ‎07-24-2013

Re: Aurora Loopback on ZC706 board

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Thanks for feedback. Indeed, I am trying to create a 2X1 lane design.

 

I could connect the master "clk_out" to the relevant "clk_in" but I want to drive the slave interface with a different GT_DIFF_REFCLK. Is that possible, having this configuration? This is to replicate the different SMA clock on the other board of the example, which I plan getting around using the FMC_LPC clocks on J5, namely (MGTREFCLK0P_111 and MGTREFCLK0N_111).

 

I hope this design choice is not absolutely absurd?

Thanks in advance.

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Moderator
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Registered: ‎02-16-2010

Re: Aurora Loopback on ZC706 board

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Yes. It is possible to apply different REFCLKs to the Master and Slave cores.

The use case is proper one only.
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Visitor
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Registered: ‎07-24-2013

Re: Aurora Loopback on ZC706 board

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How to address "drp_clk_in" ?

 

 

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Community Manager
Community Manager
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Registered: ‎07-23-2012

Re: Aurora Loopback on ZC706 board

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Hi,

drp_clk_in can be common for both master and slave and it can come from external source.

Regards,
Krishna
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