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Explorer
Explorer
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Registered: ‎08-12-2019

BIST fail on VCU118 board

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we test BIST on BIT GUI based on xtp439 & xtp449,there are many errors, log is as shown in the following:

 

Info: BIST test started...

Info: The test will take 0 hours, 02 minutes, and 18 seconds. 0:02:18

Info: This step started at: 2020-05-18 17:35:11

Info: This step started at: 2020-05-18 17:35:11

****** Vivado Lab Edition v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ipi.tcl}
# open_hw
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2019.1
**** Build date : May 24 2019 at 15:13:31
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.




# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308AAFBD0
# set_property PROGRAM.FILE {[pwd]/../bitstream/ipi_app_basic.bit} [lindex [get_hw_devices] 0]
# program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:26 ; elapsed = 00:00:25 . Memory (MB): peak = 235.352 ; gain = 0.000
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308AAFBD0
# disconnect_hw_server localhost:3121
# close_hw
****** Webtalk v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source C:/vcu118_bit/tests/VCU118/.Xil/vivado_lab-3776-xuzhenganjy-mb/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'C:/vcu118_bit/tests/VCU118/.Xil/vivado_lab-3776-xuzhenganjy-mb/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Mon May 18 17:35:53 2020. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado_Lab/2019.1/doc/webtalk_introduction.html.
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 95.133 ; gain = 0.000
INFO: [Common 17-206] Exiting Webtalk at Mon May 18 17:35:53 2020...
close_hw: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 235.352 ; gain = 0.000
INFO: [Common 17-206] Exiting vivado_lab at Mon May 18 17:35:53 2020...
step finished

Info: This step started at: 2020-05-18 17:35:54
Writing: '33'

Info: This step started at: 2020-05-18 17:35:55
Writing: '55'

Info: This step started at: 2020-05-18 17:35:56
Writing: '99'

Info: This step started at: 2020-05-18 17:36:36
Writing: 'AA'

Info: This step started at: 2020-05-18 17:37:16
Writing: 'CC'

Info: This step started at: 2020-05-18 17:37:17
Writing: 'FF'

Info: This step started at: 2020-05-18 17:37:18
Writing: 'GG'

step finished

Error: Could not find regular expression in step 0 of test 12 - "(.*)All\s+Tests\s+Complete:\s+IIC\s+PASSED"

Error: Could not find regular expression in step 0 of test 12 - "(.*)Completed\s+IPI\s+Timer\s+Example"

Error: Could not find regular expression in step 0 of test 12 - "(.*)###\s+DDR4\s+Memory\s+Test\s+finished\s+successfully\s+###"

Error: Could not find regular expression in step 0 of test 12 - "(.*)AXI\s+BRAM\s+test\s+iteration\s+#1\s+has\s+PASSED!"

Error: Could not find regular expression in step 0 of test 12 - "(.*)Clocking\s+Test\s+Passed"

Error: Could not find regular expression in step 0 of test 12 - "(.*)FMC\s+LVDS\s+Test\s+passed"

Error: Could not find regular expression in step 0 of test 12 - "(.*)System\s+Monitor\s+Example\s+passed!"

Error: Could not find regular expression in step 0 of test 12 - "(.*)The\s+Current\s+Temperature\s+is\s+[2-4]\d.\d\d\d\s+Centigrades"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Fail
Info: Result for step 3: Fail
Info: Result for step 4: Fail
Info: Result for step 5: Fail
Info: Result for step 6: Fail
Info: Result for step 7: Fail
Info: Result for step 8: Fail

Info: The test took 0 hours, 02 minutes, and 18 seconds. 0:02:18

 

many people found the same problem as me in xilinx forum, but xilinx did not find any solution? why?

what is the reason? how to fix ?

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Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎06-13-2018

Re: BIST fail on VCU118 board

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3 Replies
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Xilinx Employee
Xilinx Employee
261 Views
Registered: ‎06-13-2018

Re: BIST fail on VCU118 board

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Hi @hotsauce_xu :

Share clear picture of Board when powered On. What is the board Rev? Which version of BIT (v7.0, v8.0,v9.1 etc.) are you trying?
Share a screenshot of the BIT GUI when you are running the tests.
Also, can you try BIST separately by following instructions given in XTP453?

 

Thanks,

Priyanka

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Explorer
Explorer
216 Views
Registered: ‎08-12-2019

Re: BIST fail on VCU118 board

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we have check power on status with other boards, the LED status is the same as other boards.
board revision is REV 2.0.
BIT version is 9.1

I have a question that XTP453 is used for BIST when we use the board first time?
we had used the boards for over 5 months, we had download bin files many times on flash, so chould we run BIST as XTP453 ?


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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: BIST fail on VCU118 board

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