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Explorer
Explorer
813 Views
Registered: ‎02-27-2018

CMOS standard FPGA

Hello,

 

I am using an Artix 7 FPGA.

I need to receive 3 signals from an ADC (SPI link) and output one. They are CMOS inputs and outputs.

I also need to output 16 CMOS signals to a NI DAQ

But i don't know which parameters to look to see if it is compatible with LVCMOS_25 standards

Due to my design i can only use LVCMOS_25 for both inputs and outputs of the FPGA.

Here are the parameters for both the ADC (SPI)  and the NI DAQ.

 

cmos.png
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5 Replies
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Explorer
Explorer
811 Views
Registered: ‎02-27-2018

 
CMOSNI.png
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Advisor
Advisor
787 Views
Registered: ‎04-26-2015

The challenge is going to be the maximum voltage into an FPGA pin. For an LVCMOS25 input, the maximum input voltage for a pin is 2.8V.

 

The LM98640 will probably output very close to 3.3V (the true maximum isn't specified, but at zero current it's definitely going to be over 3V).

 

The NI DAQ is probably 3.3V too, but if you add pull-up resistors (or use the FPGA internal ones) to 2.5V then you'll be able to run the DAQ I/O in open-collector mode. This solves the problem, but it'll limit the speed you can achieve.

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Explorer
Explorer
696 Views
Registered: ‎02-27-2018

If an input comes to an FPGA at 3,3 V on a pin that has the standard LVCMOS25 will it damage the FPGA?

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Explorer
Explorer
692 Views
Registered: ‎02-27-2018

Is it from this figure that we can see that the maximum input voltage for a pin is 2.8V?

dckintex.png
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Advisor
Advisor
683 Views
Registered: ‎04-26-2015

Correct. If you have a pin expecting LVCMOS25 (and therefore using VCCO = 2.5V) then above 2.8V will put you above the rated voltage.

 

The absolute maximum rating (Table 1 in DS181) is VCCO + 0.55, or 3.05V. This results in three regions:

 

Below 2.8V - no damage, correct operation is guaranteed

2.8V to 3.05V - won't cause damage, but not guaranteed to work correctly

Above 3.05V - permanent damage occurs

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