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Visitor wenshh3
Visitor
552 Views
Registered: ‎04-09-2018

Can't find KCU105 QSPI pin 'sck' assignment

In Vivado, there is an error:

 "[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 132 logical ports have no user assigned specific location constraint (LOC). "

And we can find that in the IO planning part:

 

According to UG917,

123.png

and a note is below the table:

1. CCLK is a dedicated pin and does not require an IOSTANDARD or LOC attribute.

At the same time, we can't find the pin "AA9" in I/O planning board. 

 

So, this the question, if we don't assign the specific location constraint, there is an error, if we want to assign specific location constraint, we can't find the suggested pin num.

What should I do?  Thank you for your answer.

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3 Replies
Moderator
Moderator
518 Views
Registered: ‎09-18-2014

Re: Can't find KCU105 QSPI pin 'sck' assignment

Wenshh3,

 

So what exactly are you trying to do here with the CCLK pin? Did you assign a net to this FPGA pin? This is a dedicated configuration pin! Not usable as user IO! The tools shouldn't throw this error unless you are trying to access the SPI device post config. If that is the case you will need to instantiate the STARTUPE3 block in your design. Also, it can only be used as an output.  

 

 

Regards,

T

 

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Visitor wenshh3
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505 Views
Registered: ‎04-09-2018

Re: Can't find KCU105 QSPI pin 'sck' assignment

I just want to read data from flash, Mircoblaze-SPI-Flash.  Also, I don't know how to instantiate the STARTUPE3 block, it is the name of one IP block or?  

And here are my block design and SPI setting: 

1523344330(1).png

1523344413(1).png

 

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Visitor wenshh3
Visitor
463 Views
Registered: ‎04-09-2018

Re: Can't find KCU105 QSPI pin 'sck' assignment

 

 

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