01-02-2018 02:30 AM
We are designing a custom board (design based on ZC706) using DDR- MT41J256M8DA-125:K
Since Vivado doesn't support our DDR part no , we are selecting the option "User Input" as per the below pic.
To configure DDR using Vivado since our custom board DDR- MT41J256M8DA-125:K is not supported by Vivado following parameters are needed
(1) Length (mm) ==> As per our understanding https://www.xilinx.com/support/answers/46778.html that this value is fixed for a given Zynq SOC.
(2) Package Delay(ps)
(3) Propagation delay(ps/inch)
From PCB design we got the propagation delay (in MILS) for the following signals:
From the above parameters, kindly request some inputs on how to calibrate our DDR.
01-05-2018 05:05 PM - edited 01-05-2018 05:06 PM
The Length attribute is the average trace length on the PCBA for that signal group.
The Package Delay attribute comes from the selected Zynq device. If the table isn't automatically populated then you can get the pin propagation times by opening a synthesized design and in either the IO Ports or Package Pins view right click in the area, select "Export I/O Ports", select CSV, and then press OK. When you open the CSV file you'll see the PS memory interface pins in the "Site Type" column starting with "PS_".
The propagation delay (ps/in) is derived from your board stackup. If you have it in ps/in then you can convert to mils by dividing the ps/in value by 1000 since there are 1000 mils in an inch.