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7,183 Views
Registered: ‎02-01-2009

Custom Board Unconnected Pins

Hi,

 

I am Implementing the Spartan 3 custom board.  I have Some Points as to clear,

 

device I am using is XC3S50-4PQ208.

 

Out of total 124 IOs  I am using only 100.

 

Also there are some pins of FPGA which are internally not connected.

 

1. What to do with unused pins from FPGA in design (On PCB)

 

2. Where to connect these pins.

 

3. If I will keep them Floating will Noise picking problem come.

 

Thanks and regards

 

Ravikant 

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Scholar
Scholar
7,169 Views
Registered: ‎02-27-2008

r,

 

If the pin is unconnected internal to the FPGA package, do not connect it to anything on your pcb.


If the pin is unused by your design, also do not connect it to anything on your pcb.  The tools will instantiate an internal pullup on all unused IO pins, you do not have to worry about it, we take care of it for you.  Also, no harm is done to any input pin that is used, and left floating.  Noite sure what "noise" issues you have had in the past, but the FPGA device is designed to handle intermediate voltages on all IO pins asa that is normally present in many applications.

 

It is very useful to take a number of unused IO pins, and wire them to a header, or a pin field, so that when you need to debug, you may easily route a signal out to one of these spare pins.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Newbie
6,635 Views
Registered: ‎08-26-2010

Hello ,

 

Is that the same case for Virtex 6 with dual purpose pins?

 

I am asking that because the common advise is to connect unused inputs to the digital ground.

 

Regards,

 

Nissim

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Scholar
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Registered: ‎02-27-2008

Nissim,


Dual purpose pins have a configuration function before configuration is complete.  So these pins must be tied to whatever they need to be tied to (ground, or pulled up) to provide the proper function before and during configuration.  Once configured, you then need to be sure you do not use them in your design (as they may be grounded).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎12-29-2009

Hi,

 

I find this forum topic closest to my problem so i decided to write here and aviod creating unnecessary posts..

 

Anyways, I have few questions about designing PCB for my Spartan 6 LX150t FGPA. Using package guide, configuration guide and pcb guide, i managed to find out what to do with some of the pins, but im still not sure about some other ones.

 

1- About the tranciever part, if im not usiing it, would be ok to ignore it? namely unconnect the pins? even its power and clk?

2- In the multifuntional pins, since im using JTAG for pragramming i just set M1M0=11 (serial configuration) and again the address bus, data bus, and almost all pins in this category (multifuntional) are unconnected in my design. Would this be ok?

3- There's a P-GCLK and a N-GCLK. i can't understand why it's differential and i've used only P leaving N unconnected. Is this ok or i need to do something about it?

 

4- Also a different kind of question, by my understanding, after the power up and reset and ... FPGA should stall the configuration process, without entering any deadlock or dangerous state for device, because there is no serial/parallel inputs ready till i activate the JTAG seqeunce. am i right? or im missing something here?

 

I'd be so thankful if you can answer my questions...

 

Regards,

Babak

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Scholar
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Registered: ‎02-27-2008

Babak,,

 

I will attempt to provide some answers:

 

1- About the tranciever part, if im not usiing it, would be ok to ignore it? namely unconnect the pins? even its power and clk?

 

In the GTP Users Guide, unused pins are dealt with.  I belive all analog gorunds must be grounded (to any convenient ground), and all supply pins should also be connected to a power or ground (see the guide).  Everything else leave unconnected...

 

2- In the multifuntional pins, since im using JTAG for pragramming i just set M1M0=11 (serial configuration) and again the address bus, data bus, and almost all pins in this category (multifuntional) are unconnected in my design. Would this be ok?

 

Yes, i already answered this above in this thread.  Mode pins get connected to Vcco, or ground, along with the other dedicated pins.  Dual-use pins are not needed for JATG, so they can be left unconnected.

 

3- There's a P-GCLK and a N-GCLK. i can't understand why it's differential and i've used only P leaving N unconnected. Is this ok or i need to do something about it?

 

The GCLK input pins, if programmed for a differential standard, use two pins, one for the +, and one the the - of the differential pair.  If unused, then they are like any other IO pin.

 

4- Also a different kind of question, by my understanding, after the power up and reset and ... FPGA should stall the configuration process, without entering any deadlock or dangerous state for device, because there is no serial/parallel inputs ready till i activate the JTAG seqeunce. am i right? or im missing something here?

 

I do not understand the question.  If the FPGA stalls while trying to configure, you will need to try to configure it again.  Nothing "bad" happens.  Nothing is at risk of being damaged.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
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Registered: ‎12-29-2009

Thanks alot Austin,i got all the answers needed,

 

Just about the last part, i meant because as i mentioned i'm not using Serial or Parallel mode for configuration and JTAG is what i'm going to use, FPGA being stalled won't cause 1- any damage, which you mentioned it won't and 2- it can be reset by the JTAG commands which i imagine it would then

 

Regards,

Babak

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