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4,708 Views
Registered: ‎02-01-2009

Custom board design using Spartan 3A (XC3S50AFT256) device

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Please can anyone suggest the design for power supply for designing custom board for spartan 3a device.

 

core vtg is 1.2v  and Vccaux is 2.5v and Vcco is 3.3v

 

till time i got the solution using ST Micros LD1117.

 

is there any special requirement please let me know.

 

any valuable guidence is highly appriciated.

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5,803 Views
Registered: ‎02-01-2009

Hi Austin

 

thanks alot for all that information I really got my working systems power requirement and 

 

with that i can conclude that not more than 500 mA current is required to drive IO's of 

 

FPGA so that can I design the Power circuit using LD1117XX12 for 1.2v , LD1117XX25 for 2.5v and 

 

LD1117XX33 for 3.3v. As per specifications 800mA is typical current sourcing capablity of LD1117XX.

 

thnanks and regards.

 

Ravikant.

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Scholar
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Registered: ‎02-27-2008

k,

 

http://www.xilinx.com/products/design_resources/power_central/index.htm

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
5,804 Views
Registered: ‎02-01-2009

Hi Austin

 

thanks alot for all that information I really got my working systems power requirement and 

 

with that i can conclude that not more than 500 mA current is required to drive IO's of 

 

FPGA so that can I design the Power circuit using LD1117XX12 for 1.2v , LD1117XX25 for 2.5v and 

 

LD1117XX33 for 3.3v. As per specifications 800mA is typical current sourcing capablity of LD1117XX.

 

thnanks and regards.

 

Ravikant.

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Registered: ‎02-01-2009

please it will be great if some one help me in designing Bypass / Decoupling capacitors.

 

as maximum working frequency of I/O pins is around 50 KHz and clock taken input from crystal is 24Mhz.

 

it will be great if the simplest format to accomplish this task .

 

thanks and regards

 

Ravikant

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Scholar
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Registered: ‎02-27-2008

k,

 

Generally, the frequency of operation is unimportant, as it is the rise and fall times of the IO pins which determine the current spikes.

 

A mix of .001uF, .01uF, and .1uF is appropriate (one cap per Vcc pin for core, aux, and IO).

 

For each of the three supplies, at least one 330uF cap is suggested, for low frequency filtering.

 

Austin Lesea
Principal Engineer
Xilinx San Jose