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Explorer
Explorer
12,899 Views
Registered: ‎11-19-2010

DDR PCB layout rules

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I am designing a PCB with Artix and DDR2 (eventually DDR3). I found a number of application notes on how to layout the PCB, watch out for impedance, EMI and sI, etc but I haven't found a clearly defined whole set of length match rules. Is there such thing? Out of my desperation I had a look at the SP605 gerber files and noticed lengths between 900 and 1400 mils. Is then +- 300 mils a margin I can stick to? Does anybody know about a clear definition on this?

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Explorer
Explorer
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Registered: ‎11-19-2010

Finally I found all the answers. The reason of all those diverging and ambiguous guidelines is they are mere starting points and the ultimate validation is to be done by SI simulation and prototyping. Why don't they say it so simple and clear from the beginning then?

Anyways...

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-06-2013

Hi

 

Refer design guidelines section of below doc

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf

Regards,

Satish

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Explorer
Explorer
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Registered: ‎11-19-2010

Thanks, that's a document already had a look. Does this mean, for a DDR2, I should stick to these and only these three conditions? Somewhere else I read the CK diff pair should be te longest track, just to put an example of how many different criteria exist out there. And, how can this (below) be independent of the DDR data rate? As far as I know there are DDR2-400 as well as DDR2-1066. Are these rules for the highest?

 

1 - The maximum electrical delay between any DQ and its associated DQS/DQS# must
be less than or equal to ±5 ps.
2 - The maximum electrical delay between any address and control signals and the
corresponding CK/CK# must be less than or equal to ±25 ps.
3 - The maximum electrical delay between any DQS/DQS# and CK/CK# must be less
than ±25ps.

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Explorer
Explorer
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Registered: ‎11-19-2010

One more example of confusion:

 

UG388 page 42 gives guidelines for DDR memory interface routing.

 

"There should be a maximum of +/- 25ps electrical delay (+/- 150mil) between any DQ/DM and its associated DQS strobe."

So 25? 5?

 

And here:

 

http://forums.xilinx.com/t5/Timing-Analysis/propagation-delay-matching-for-DDR2-memories/td-p/164980

 

The Expert Contributor Bob Elkind says (writes):

 

"I don't know the source of the 50pS timing difference between the two paths, but 50pS is inconsequential.  I wouldn't worry about it"

 

 

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Explorer
Explorer
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Registered: ‎11-19-2010
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Explorer
Explorer
20,502 Views
Registered: ‎11-19-2010

Finally I found all the answers. The reason of all those diverging and ambiguous guidelines is they are mere starting points and the ultimate validation is to be done by SI simulation and prototyping. Why don't they say it so simple and clear from the beginning then?

Anyways...

View solution in original post

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