01-22-2019 11:15 AM
Looking at AR# 71209 represents two types of DDR4 component for PL side of the UltraScale+ devices, i.e., x8 and x16. Also, looking at page 33 of ZCU106 User Guide indicates that the Xilinx has used x16 topology to configure DDR4 component of the PL side.
I have two questions :
1. Is there any specific reason that Xilinx has chosen x16 topology? Is there restriction that forces using this configuration?
2. What does Bank group in AR# 71209 stand for?
Thanks in advance for your kind replies and helps.
01-22-2019 08:24 PM