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daryon
Adventurer
Adventurer
650 Views
Registered: ‎08-30-2018

DDR4 Component Structure in ZCU106; Why x16??

Dear all,

 

Looking at AR# 71209 represents two types of DDR4 component for PL side of the UltraScale+ devices, i.e., x8 and x16. Also, looking at page 33 of ZCU106 User Guide indicates that the Xilinx has used x16 topology to configure DDR4 component of the PL side.

I have two questions :

1. Is there any specific reason that Xilinx has chosen x16 topology? Is there restriction that forces using this configuration?

2. What does Bank group in AR# 71209 stand for?

 

Thanks in advance for your kind replies and helps.

Best,

Daryon

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andresb
Xilinx Employee
Xilinx Employee
604 Views
Registered: ‎06-21-2018

Hi daryon,

I'm not a moderator, but I would try posting your question in the Memory board:

https://forums.xilinx.com/t5/Memory-Interfaces/bd-p/MIG

Thanks,
Andres

 

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daryon
Adventurer
Adventurer
567 Views
Registered: ‎08-30-2018

Dear @andresb,

 

Thanks for your great suggestion. I have reposted my question there.

 

Bests,

Daryon 

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