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Explorer
Explorer
8,944 Views
Registered: ‎09-04-2015

DDR4 IO standard and Termination used in VCU108 EVM

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Hi,

 

As per http://www.xilinx.com/products/design_resources/mem_corner/ddr4.htm link, the IO standard supported by DDR4 is POD. However, we see that in VCU108 EVM, the address and control lines of DDR4 are pulled to 0.6V supply, which is required for HSTL/SSTL standard. These are required to be pulled to 1.2V when POD standard is used. Can you please clarify what standards are supported by DDR4 and what has been used in VCU108 EVM.

 

Regards,

Raja

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Xilinx Employee
Xilinx Employee
16,020 Views
Registered: ‎07-11-2011

Re: DDR4 IO standard and Termination used in VCU108 EVM

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@raja1

 

@tud_hartmann is correct, additionally,  MIG Ultrascale DDR4 uses SSTL12 for Address/Control byte groups and POD12_DCI for Data byte groups.  The Vref voltage for SSTL12 is 0.6V.  TheVref voltage for POD12_DCI is 0.84V.  But a bank is shared between these incompatible IO standards,  while the Vref voltages do not match for SSTL12 and POD12_DCI, Address/Control are outputs only and therefore do not require Vref.  Only POD12_DCI on data requires the internal vref.  As such, the xdc MIG generates required constraints 

 

Hope this helps

 

-Vanitha

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Adventurer
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8,937 Views
Registered: ‎02-24-2012

Re: DDR4 IO standard and Termination used in VCU108 EVM

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In DDR4 data termination is against VDDQ, but command/address termination is VDDQ/2. DDR3 terminated both to VDDQ/2.

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Adventurer
Adventurer
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Registered: ‎02-24-2012

Re: DDR4 IO standard and Termination used in VCU108 EVM

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Additionally, the IO standard is not really important as long as the driver can handle the speed (drive strength) and you can achieve the correct signal levels on the PCB.

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Xilinx Employee
Xilinx Employee
16,021 Views
Registered: ‎07-11-2011

Re: DDR4 IO standard and Termination used in VCU108 EVM

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@raja1

 

@tud_hartmann is correct, additionally,  MIG Ultrascale DDR4 uses SSTL12 for Address/Control byte groups and POD12_DCI for Data byte groups.  The Vref voltage for SSTL12 is 0.6V.  TheVref voltage for POD12_DCI is 0.84V.  But a bank is shared between these incompatible IO standards,  while the Vref voltages do not match for SSTL12 and POD12_DCI, Address/Control are outputs only and therefore do not require Vref.  Only POD12_DCI on data requires the internal vref.  As such, the xdc MIG generates required constraints 

 

Hope this helps

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post