I am looking for FPGA board for 500 MSPS parallel LVDS ADC(ADS5463) and DAC(DAC3152) interface. I am looking at ZC706 as one of the options but not sure yet.
The data read window for the ADC is around 800 ps (before jitter/uncertainty, signal integrity, board routing skew etc...).
If I plan to use ZC706 as my FPGA board,
What are the precautions I need to take if I plan to design and implement this system in Vivado?
What are the possible pitfalls for this implementation?
What are the other options that I should be looking at I want to implement this design successfully?