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738 Views
Registered: ‎02-14-2018

Delays related to the VCU1525 board traces

Hi ,

 

Where I can find the delay values for "board-traces" applicable for   configuration of the FPGA ( QSPI->Startup E3-> Micron on-board Flash) ? 

 

  tdata_trace_delay  ( max  and min) 

  tclk_trace_delay  ( max  and min) 

 

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Moderator
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680 Views
Registered: ‎04-12-2017

Re: Delays related to the VCU1525 board traces

Hello @raj_goutam_sf,

 

I am not sure if we document this.

But one can calculate trace length values using the Allegro file in board file section.

https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html#documentation

You will require Allegro tool from cadence to read this file.

 

It will be possible then to calculate the trace delay if signal speed and trace length is known.

 

Hope this helps.

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665 Views
Registered: ‎02-14-2018

Re: Delays related to the VCU1525 board traces

Thanks @kvasantr ,

 

These delays are used to constrained the path associated with BPI/SPI  FLASH Memory for Post-Config Access. 

These delays are mentioned in Xilinx App Note(s),meant for particular board(s).

 

For-Example : xapp1282 ,  Page 28 

 

---------------------------------------------

#### Trace delays for VCU108 board
set tdata_trace_delay_max 0.25
set tdata_trace_delay_min 0.25
set tclk_trace_delay_max 0.2
set tclk_trace_delay_min 0.2
set startup_delay_max 7.000
set startup_delay_min 1.350
set board_del_max 1.000
set board_del_min 0.500

------------------------------------------

 

So these delays are documented (You may check for other Boards) !!!!

 

Now downloading a third-party tool (may not be free ? )  to calculate these delays are not an easy task  , instead of  these delay should be a part of documentation related to the VCU1525 Board.

 

Thanks ,

Raj

 

 

 

 

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Moderator
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653 Views
Registered: ‎04-12-2017

Re: Delays related to the VCU1525 board traces

Hello @raj_goutam_sf,

 

Thank you for pointing this out. 

 

Unfortunately this values are not documented for  VCU1525. 

Trace delay values for this boards arre calculated as per PCB design guidelines.

 

To get the trace lengths for this board you can use the Allegro free file viewer.

https://www.cadence.com/content/cadence-www/global/en_US/home/tools/allegro-downloads-start.html

 

Please follow UG949 and this https://web.ewu.edu/groups/technology/Claudio/ee260/LabDocuments/pcb_xilinx.pdf for more help.

In such case considering package flight time will be necessary for aaccuracy.

refer https://www.xilinx.com/support/answers/55697.html

 

Thank you.

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