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Visitor schroeca
Registered: ‎06-27-2012

Design support for noise reduction FMC



I would like to build an RF interface board for the ML605. I'm currently working on a daughter board for the FMC-LP connector which will contain a Multi-Band ISM transceiver with an 4 Bit sigma-delta ADC output. 


My Problem:

The Receive Part of the used IC is very sensible to power supply noise / ripple and the ML605 produces lots of noise.

Is there any App-Note / Design Guide existing on how to handle the that. 

E.g.. Which decoupling caps? Layout recommendations? Example designs?



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Scholar austin
Registered: ‎02-27-2008

Re: Design support for noise reduction FMC



No, there is no such resources.  And, I would suggest that I have never seen any such app notes, nor guides, for such a task, ever.

In RF design, with the proper E&M modeling tools (for 3D simulations), one can see what needs to be done, and if you have the experience, you then attempt to do it.

I have built many such systems, spanning microwave radio systems, digital modems, optical systems, so on and so forth.  The techniques I used were learned from my own mistakes, from other's mistakes, and by looking at similar products, and how they were constructed.


I would suggest that getting a radio front end anywhere within a 100 meters of the demonstration FPGA boards, is a disaster.


One has to create Faraday cages (shielding) around the digital sections, to remove the noise and E&M fields from the receiver electronics.


The construction of the wireless products today:  bluetooth, wifi, cell-phones, GPS receivers, etc. are marvels of engineering precisely because they make it look so easy, when it has actually been very very hard, with many mistakes made along the way, and many prototype pcb's thrown away because they just didn't work.

Hire a RF design expert, or be prepared to learn how (the hard way by making every mistake possible),





Austin Lesea
Principal Engineer
Xilinx San Jose
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