cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
j0n
Adventurer
Adventurer
566 Views
Registered: ‎09-28-2017

Difficulties with AC701 MIG 7 (setting 400 MHz clock clock period)

Jump to solution

Hi all, I have an AC701 evaluation board from Xilinx and running a basic MIG7 configuration. Relevant MIG7 configuration settings are as follow:

clock period = 400 MHz 
memory part= MT41J128M8XX-125 (from the drop down menu)
data width = 16
Number of bank machines = 4

Input clock period = 200 MHz
System clock: no buffer
Reference clock: Use system clock 

The issue is that when using clock period of 400 MHz calib done is never high. When I reduce the clock period to 326.26 MHz in MIG configuration, then calib done is high. No other changes are made other than the input clock period which is still around 200 MHz so system clock is still used the same way. 

I am pretty sure that AC701 should support 400 MHz clock period so would appreciate any help with this. 

1 Solution

Accepted Solutions
katsuki
Xilinx Employee
Xilinx Employee
544 Views
Registered: ‎11-05-2019

 

Hello,

 

Is this result when operating on AC701?

The memory installed in the AC701 is SO-DIMM, and the model name is MT8JTF12864HZ-1G6G1. Please refer to XTP225.

The MT41J128M8XX-125 that you specify is a component memory, so it will not work.

 

AR#63234 is a performance estimation guide by simulation and uses MT41J128M8XX-125.

 

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

2 Replies
katsuki
Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎11-05-2019

 

Hello,

 

Is this result when operating on AC701?

The memory installed in the AC701 is SO-DIMM, and the model name is MT8JTF12864HZ-1G6G1. Please refer to XTP225.

The MT41J128M8XX-125 that you specify is a component memory, so it will not work.

 

AR#63234 is a performance estimation guide by simulation and uses MT41J128M8XX-125.

 

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

View solution in original post

j0n
Adventurer
Adventurer
496 Views
Registered: ‎09-28-2017

Hi @katsuki,

Thanks I don't know how I missed the SO-DIMM specification. I changed the configuration specifying the correct SO-DIMM now the calib done signal is high as expected. Thanks!