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Explorer
Explorer
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Registered: ‎04-06-2017

Does VREF pin have to be connected to a reference when SSTL standards are used as output of FPGA?

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Does VREF pin have to be connected to a reference of this bank when SSTL standards are used as output of FPGA?
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Explorer
Explorer
675 Views
Registered: ‎04-06-2017
No,
VREF pins are not needed to connect to reference voltage for ouput standards

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Highlighted
Explorer
Explorer
676 Views
Registered: ‎04-06-2017
No,
VREF pins are not needed to connect to reference voltage for ouput standards

View solution in original post

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