cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
vividsparks
Visitor
Visitor
402 Views
Registered: ‎03-16-2015

Dollar-sign not supported

Jump to solution

Hello All,

I am trying to synthesize some .sv files  which has:

AXI_Command sh_cl_wr_cmds[$];
AXI_Data sh_cl_wr_data[$];
AXI_Command sh_cl_rd_cmds[$];
AXI_Data cl_sh_rd_data[$];
AXI_Command sh_cl_b_resps[$];

I am getting following error:

[Synth 8-27] dollar-sign operator not supported.

Can you please assist on this?

Thanks,

-Vijay

 

 

0 Kudos
1 Solution

Accepted Solutions
baciek
Contributor
Contributor
347 Views
Registered: ‎06-22-2018

In HDL languages there are some constructs that can be synthesized and there are some that cannot (for example delays, force/release etc.) SystemVerilog is a special kind'a special language, because as an extention of Verilog it adds almost none sythesizable constructs. Queues, dynamic arrays, classes etc. can't be synthesized and "put into the hardware"

View solution in original post

0 Kudos
4 Replies
vividsparks
Visitor
Visitor
377 Views
Registered: ‎03-16-2015

 I am using Vivado 2019.1

0 Kudos
baciek
Contributor
Contributor
376 Views
Registered: ‎06-22-2018

Hello,

type variable[$]; 

creates queue (FIFO) of infinite size. It is non-synthesizable subset of SystemVerilog - it was meant to be used in simulation only.

Best regards.

Maciej

vividsparks
Visitor
Visitor
371 Views
Registered: ‎03-16-2015

I am sorry, not clear, like this?

type variable[$];

AXI_Command sh_cl_wr_cmds[$];

AXI_Data sh_cl_wr_data[$];
AXI_Command sh_cl_rd_cmds[$];
AXI_Data cl_sh_rd_data[$];
AXI_Command sh_cl_b_resps[$];

 

0 Kudos
baciek
Contributor
Contributor
348 Views
Registered: ‎06-22-2018

In HDL languages there are some constructs that can be synthesized and there are some that cannot (for example delays, force/release etc.) SystemVerilog is a special kind'a special language, because as an extention of Verilog it adds almost none sythesizable constructs. Queues, dynamic arrays, classes etc. can't be synthesized and "put into the hardware"

View solution in original post

0 Kudos