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Observer
Observer
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Registered: ‎03-19-2012

FMC150 and ML605 board in System Generator.

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I would like to use ML605 with the ADC from FMC150 card - in an application as simple as sampling a sinewave for example and displaying the result on a scope in simulink. I need to preform a HW-cosim using point-to-point ethernet using a free running clock; for which I have done the output interface using a shared memory configured as FIFO. 

 

I went through the datasheets for the ADS62P49 and CDCE72010 , I've also read the vhdl code from the getting started reference design for the ML605 DSP kit, extracted what I need for the operation of the ADC. 

 

So now I need to import the vhdl file (for ADC interface) into a blackbox in sysgen.

 

1-How to set the constraints for this (ADC) block ? 

(i.e. how to set the clk_ab_p, clk_ab_n, cha_p and cha_n in the getting started reference design for example to the corresponding ports of the FMC150?  - like adding a UCF file )

 

2-Is it possible to import the mmcm  blocks?  and how to make the clock of my design an output of the mmcm ? 

 

3-Is it possible to get rid of the mmcm blocks in the getting started reference design if I use a sampling frequency equal to the clock frequency (say 100 MSPS  and 100 MHz clock) ? 

 

4-If there is any simpler way to do this, please provide me with your suggestions. 

 

Thanks in advance,

Ahmed.

 

 

 

 

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Observer
Observer
7,417 Views
Registered: ‎03-19-2012

Hi Gabriel,

I found an alternative solution for this, 

what I did is defining a new implementation target in system generator - in which you can select your clock port. Then I added the outputs of the ADC as non memory mapped ports. and I added a blackbox only for the IDDR buffer, for turning the DDR format of the LVDS_25 buffer into SDR. 

 

However I am facing currently a problem of how to define a port in system generator as LVDS. as when I add this LVDS buffer as a blackbox, the system generator would give me an error , because it would infer the input port connected to this buffer as a single ended input buffer , and gives me an error that It is not allowed to have 2 input buffers connected in a row. 

 

and when I try to specify that in the UCF file associated with the target that I defined, I get an error that the input non-memory mapped port is single ended and the UCF staes the constraint that it should be differential.

 

I just posted this porblem here : http://forums.xilinx.com/t5/DSP-Tools/LVDS-buffer-for-sysgen/td-p/221831

but so far no answer.

 

any other solutions in mind ? 

 

Best regards,

Ahmed.

 

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5,850 Views
Registered: ‎03-01-2012

Hello Ahmed,

 

Did you carry on with this idea? I am now facing exactly the same problem, but I am about to move away and try an alternative solution for my problem..

 

Regards,

Gabriel

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Highlighted
Observer
Observer
7,418 Views
Registered: ‎03-19-2012

Hi Gabriel,

I found an alternative solution for this, 

what I did is defining a new implementation target in system generator - in which you can select your clock port. Then I added the outputs of the ADC as non memory mapped ports. and I added a blackbox only for the IDDR buffer, for turning the DDR format of the LVDS_25 buffer into SDR. 

 

However I am facing currently a problem of how to define a port in system generator as LVDS. as when I add this LVDS buffer as a blackbox, the system generator would give me an error , because it would infer the input port connected to this buffer as a single ended input buffer , and gives me an error that It is not allowed to have 2 input buffers connected in a row. 

 

and when I try to specify that in the UCF file associated with the target that I defined, I get an error that the input non-memory mapped port is single ended and the UCF staes the constraint that it should be differential.

 

I just posted this porblem here : http://forums.xilinx.com/t5/DSP-Tools/LVDS-buffer-for-sysgen/td-p/221831

but so far no answer.

 

any other solutions in mind ? 

 

Best regards,

Ahmed.

 

View solution in original post

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