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Observer
Observer
7,721 Views
Registered: ‎04-15-2010

Generating GTX clks in ML605

Hi,

 

There's something simple I don't understand, when i generate Temac/Aurora Core in the example design UCF file, 2 differencial clocks should be created.

In the UCF file I get the following constrains:

NET GTXQ4_P  LOC=H6; 
NET GTXQ4_N  LOC=H5; 
...
INST *aurora_module_i/gtx_wrapper_i/GTXE1_INST/gtxe1_i LOC=GTXE1_X0Y18;

How are the clocks created? (are there an internal clocks connected to H5/H6?)

How does the last line mentioned connects the TX/RX ports to the appropriate SMA connectors?

 

12 Replies
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Xilinx Employee
Xilinx Employee
7,703 Views
Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

Aurora only uses a single reference clock, not two as you indicated.  This clock is not created or generated by the Aurora core or by the FPGA it needs to be a physical device on the board.  You UCF constraint has locations for a single reference clock that uses differerntial signalling to the H6/H5 pins.  On the ML605 board these pins are connected to a 125 MHz differential clock.

 

The GTX was located to the GTXE_X0Y18 site.  The V-6 GTX User Guide, UG366, documents this location in the 6VLX240T-FF1156 as the MGT2 in Quad 116 that uses pins D5, D6, B1, B2.  The ML605 documents that this MGT location and pins are connected to the MGT SMAs on the ML605.

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Observer
Observer
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Registered: ‎04-15-2010

Re: Generating GTX clks in ML605

If I understand right, the SMA connectors need a differential clock to be able to work.

This is the clock I've mentioned in the UCF file.

Who is responsible for creating this clock? Is it automatically created when I locate the GTX to GTXE_X0Y18 site?

 

The reason I'm asking this is that I'm not able to make my Aurora core example design to work correctly on my ML605 evaluation kit  so I'm searching for the reason for this.

 

I can't find the reason and really need some help.

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

The clock locations that you picked were for a fixed 125 MHz LVDS clock oscillator not the SMA clock inputs.

 

If you change the reference clock inputs to the SMA locations F6/F6 (MGTREFCLK1_116) then you will need to provide inputs to these SMA connectors from external equipment.

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Observer
Observer
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Registered: ‎04-15-2010

Re: Generating GTX clks in ML605

You mean that if I want to use SMA connectors for RX & TX (I want to use them with Aurora core) then I need to provide external clock for 3.125Gbps N/P?

Isn't it possible to generate this differential clock by the ML605 itself?

If so maybe this is the reason I didn't manage to make the example design to work?

 

Thanks, waiting for your reply!

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Xilinx Employee
Xilinx Employee
7,657 Views
Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

> You mean that if I want to use SMA connectors for RX & TX (I want to use them with Aurora core)

>then I need to provide external clock for 3.125Gbps N/P?

 

I never said that, please re-read my prior post.

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Observer
Observer
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Registered: ‎04-15-2010

Re: Generating GTX clks in ML605

OK, so I guess I didn't understand you right...
Did you mean that from the H5/H6 locations the design receives its reference differential clock (125Mhz) and that's OK?
There's something I still don't understand:
If I want to send and receive data using the SMA connectors with aurora protocol do I need to assign/ create constrains for the serial clock (with 3.125Gbps rate) they work with? I didn't see its generation anywhere in the ucf file.
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

> with aurora protocol do I need to assign/ create constrains for the serial clock (with 3.125Gbps

> rate) they work with?

 

When you generated the Aurora core you would have specified the data rate and the reference clock rate.  CoreGen would have used this information to correctly apply the appropriate attributes to GTX to match these inputs.

 

If you did not set the reference clock rate to 125 MHz to match the clock source attached to the H6/H5 reference clock pins then your Aurora core will not function correctly.

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Observer
Observer
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Registered: ‎04-15-2010

Re: Generating GTX clks in ML605

>CoreGen would have used this information to correctly apply the appropriate attributes to GTX to match these inputs.

Where that happens? In which file/place?

 

What is the solution in case the referance clock is not 125Mhz? In this case the clock needs to be constrained differently?

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

>>CoreGen would have used this information to correctly apply the appropriate attributes to GTX to match these inputs.

>Where that happens? In which file/place?

 

Please re-read the sentence that I wrote just before the one that you copy-and-pasted.

 

> What is the solution in case the referance clock is not 125Mhz? In this case the clock needs to be constrained differently?

 

I need to ask this at this point.  How much experience do you have with real hardware designs?

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Observer
Observer
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Registered: ‎04-15-2010

Re: Generating GTX clks in ML605

Not much, I'm a student that still learning things. If I was an expert I wouldn't ask questions in the forum for my fun.

 

What is the relevance of my experience? This forum is intended for asking questions.

 

If my questions is too silly for you you don't have to answer and I hope someone else will that my experience is not an issue for him.

 

I realy don't understand the intention of this question. You're very not customer/ user friendly and that's a shame.

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Xilinx Employee
Xilinx Employee
3,550 Views
Registered: ‎01-03-2008

Re: Generating GTX clks in ML605

> What is the relevance of my experience?

It helps myself and other determine the level of detail necessary to be able to help you.  Since you are a student it would be a lot more productive for you if you discussed some of these questions with your professor, teachers assistant or a fellow classmate.  Face to face discussions are usually a lot more productive and can cover a lot more ground faster than slow forum posts.

 

Using MGTs, TEMAC, PowerPC or PCIe hard cores is an advanced design practice.  You should be very comfortable designing with the standard FPGA logic (IOs, PLLs, BlockRAMs, CLBs, etc..) before attempting designs with these embedded blocks.

 

> You're very not customer/ user friendly and that's a shame.

I went back and re-read all of my posts in this thread and I don't understand why you would make this comment. Please point out anything that I have written that wasn't friendly. 

 

Getting back to your previous question:

 

> What is the solution in case the referance clock is not 125Mhz? In this case the clock needs to be constrained differently?

 

Clocks sources are physical components and these clock sources are not constrained because they are discrete parts with specific functionality. FPGAs do not include clock sources, but they do require them in order to operate.  The clock sources must be connected to the FPGA through the IO pins that are defined to accept clock inputs.  

 

In the case of MGT (GTX) blocks the reference clock input pins are dedicated IOs and cannot be used for any other purpose. The FPGA designer must generate IO placement constraints to identify the specfic pins that the external reference clock source is connected to on the FPGA.  The reference clock IO placement constraints must match with the physical PCB design as all IO placement constraint must match with the physical PCB for correct operation.

 

The FPGA designer should also define a PERIOD constraint for the reference clock input.  This PERIOD constraint will be used for timing analysis when the design is placed and routed, but it will have no other effect on the design.

 

When you create a MGT (GTX) design the external reference clock frequency and the desired data rate must be known.  These values must be used to correctly set the values for many attributes of the MGT (GTX).  The values can be set explicitly by the designer following the information the MGT User Guide for the FPGA family that is being used or if CoreGen is creating a core that uses a MGT these values will be set when the core is generated based on the values that the designer entered during the core customization steps.

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Instructor
Instructor
3,549 Views
Registered: ‎07-21-2009

attitude check

Not much, I'm a student that still learning things. If I was an expert I wouldn't ask questions in the forum for my fun.

What is the relevance of my experience? This forum is intended for asking questions. If my questions is too silly for you you don't have to answer and I hope someone else will that my experience is not an issue for him. I realy don't understand the intention of this question. You're very not customer/ user friendly and that's a shame.

Whoa!  Drop the defensive attitude, Mr. 309562908!  Ed McGettigan (McGett) is knowledgeable, patient, and quite customer friendly.  He's trying to help you, and it is not in your interest to attack him or insult him.  You may be frustrated, but you're picking the wrong target.

 

Take a deep breath, and then start over.

 

It is entirely reasonable to ask you about your experience level

  • with FPGAs
  • with HDL language
  • with digital logic / hardware design
  • with circuit board design
  • with the ISE toolset

All of these are important considerations for asking the right questions and providing guidance which is helpful and understandable for you.

 

You may be a brilliant student, but experience counts for much.  Even if my IQ is 180, I don't have a lot of experience in car repair....  so I don't expect my auto mechanic to talk with me in the same terms he uses when he talks shop with his IQ=110 colleagues.  That's not condescending, it's a matter of being clear and patient.  If the auto mechanic started tossing around buzzwords and acronyms which are completely foreign to me, I'd get mad in a hurry, and so would you.

 

Giving you advice which is geared for your experience and background isn't insulting, it's being respectful to you.

 

-- Bob Elkind

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