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141 Views
Registered: ‎07-10-2019

Generation of higher frequency using clock generator ip core in Artix 7 Evaluation board

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Hi,

I am using Artix-7 Evaluation board where I am trying to generate 140 MHz IQ data stream from DDS core.

For this I am trying to generate 600 MHz(approax 4x of the 140MHz) from the FPGA system clock of 200MHz using Xilinx clock wizard IP core.

However this 600MHz clock output is not coming as perfect clock. It has distortion and frequency is not coming as desired.

Kindly let me know how much maximum clock can be generated in Artix 7 board? If 600MHz can not be generated then how to generate 140MHz IQ samples(any alternate solutions)?

Thanks 

Vikas

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Moderator
Moderator
136 Views
Registered: ‎08-08-2017

Re: Generation of higher frequency using clock generator ip core in Artix 7 Evaluation board

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Hi @vikas01031989 

MMCM maximum output frequency supported in Artix-7 device is  800MHz for all the speed grades. However the maximum frequency supported in the fabric is based on Maximum frequency supported by clock buffers (Fmax of BUFG).

Capture.PNG

AC701 evaluation platform has XC7A200T-2FBG676C FPGA  device , so the 600Mhz is within the specified range above.

But it is not clear to me , where are you checking the clock and how clock is forwarded from device ?

The best way to output a clock is to use an ODDR. 

However this 600MHz clock output is not coming as perfect clock. It has distortion and frequency is not coming as desired.

-> Can you please share the Oscilloscope screenshot monitoring the 600Mhz clock?

 

 

 

 

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Reply if you have any queries, give kudos and accept as solution
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3 Replies
Moderator
Moderator
137 Views
Registered: ‎08-08-2017

Re: Generation of higher frequency using clock generator ip core in Artix 7 Evaluation board

Jump to solution

Hi @vikas01031989 

MMCM maximum output frequency supported in Artix-7 device is  800MHz for all the speed grades. However the maximum frequency supported in the fabric is based on Maximum frequency supported by clock buffers (Fmax of BUFG).

Capture.PNG

AC701 evaluation platform has XC7A200T-2FBG676C FPGA  device , so the 600Mhz is within the specified range above.

But it is not clear to me , where are you checking the clock and how clock is forwarded from device ?

The best way to output a clock is to use an ODDR. 

However this 600MHz clock output is not coming as perfect clock. It has distortion and frequency is not coming as desired.

-> Can you please share the Oscilloscope screenshot monitoring the 600Mhz clock?

 

 

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
116 Views
Registered: ‎07-10-2019

Re: Generation of higher frequency using clock generator ip core in Artix 7 Evaluation board

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Hi,

Yes you are right, It was the way I was measuring it and so  distorted signal was coming on oscilloscope.

600MHz is coming clean and as per levels declared.

Thanks for sharing the table.

Regards

Vikas

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Moderator
Moderator
110 Views
Registered: ‎08-08-2017

Re: Generation of higher frequency using clock generator ip core in Artix 7 Evaluation board

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Hi @vikas01031989 

Do you have further queries around this ?  If not please close this thread by marking appropriate answer as accepted solution.

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