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Explorer
Explorer
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Registered: ‎03-16-2019

How can I change xapp1274 to haveTx and Rx in different I/O banks?

I am using Kcu105 with J22 FMC loopback board.

I want to implement xapp1274 (Asynch mode) on my board. I found out that J22 FMC loopback board has a loopback connection between banks of 68 to 67. I want to know that how can I change sources to have the desired platform for testing loopback with FMC loopback board?

I have read readme file of xapp1274 implementation, but the file and pdf don't mention how to change the design to have RX and Tx in a separate I/O banks

 

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Scholar
Scholar
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Registered: ‎03-28-2016

@behnam_2705new,

More than likely, you will need to create two implementations.  One with only the TX section and the other with only the RX section.

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com
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Explorer
Explorer
365 Views
Registered: ‎03-16-2019

do you mean that I should double instantiate Byte_Top_RxTx_Prbs  module and then select one of them for bank 67 and the other one for bank 68?

as I've seen Xilinx declare that this project is suitable for testing loop back in Kcu105 board with FMC loopback (J22) daughterboard. I need minimum change to implement AsyncDataCapture_Byte code in my board.

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