03-21-2011 04:45 AM
I designed the digital controller usin XSG blocks.It works fine.The problem is that it offerd total path delay of 33 ns.
I have Spartan 3E Board.it offers clock frequency of 50 MHz,equivalent to 20 ns.The path delay should be less than this clock period (20 ns).First I want to generate hw cosim block and then want to use it for the hardware/software cosimulation. I can't simplyfy further my algorithm to reduce the path delay. How can I solve this problem?Please help me,I am confused.
All I want to use hardware in loop and I had Spartan 3E.
03-21-2011 05:31 AM
First you can take a look at your worst case paths in the post P&R timing report and
see if there is room for improvement with better placement. If the percentage of
path due to routing is more than 50% you can usually get better results just by
using the highest effort settings. Some things that help:
Turn off equivalent register removal
Turn off resource sharing
Enable register balancing
If you really can't get the path timing lower, then you need to slow down your
clock. Just because the clock on your board is 50 MHz doesn't mean your
HW co-sim needs to run at 50 MHz. You can use a DCM to reduce the
clock speed to 30 MHz to match your worst-case delays.
03-21-2011 12:31 PM
thanks for the reply, I tried to minimize the path delay but to no avail.
"You can use a DCM to reduce theclock speed to 30 MHz to match your worst-case delays".
How can I do that in order to create hw cosim block for the system?
While declaring 3E as new compilation device,i declared the 50 MHz at Pin C9.
Cab u elaborate more comprehensively how can I use DCM to get flexible clock?
Actually inver used FPGA before.
Hope u will not mind.