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Participant mustishesap
Registered: ‎08-22-2019

How to adjust frequency of clock output of BRAM Controller IP Core?

Hi I am trying to develop a user logic which communicates vwith PC via AXI interface. In order to store data which I've collected via AXI, I use BRAM Controller IP Core of Xilinx. BRAM Controller IP core has two interfaces. One is slave axi and the other is bram ports. In my project, frequency of axi clock is 250 MHz. General view of this IP core is attached below. The document of this IP core says that output clock frequency of BRAM Ports of this IP Core is same with axi clock frequency. The problem is, when I ran the system on ILA, bram clk doesn't work. It just stays at '0'. Anyone knows how does this clk work? 


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