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Adventurer
Adventurer
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Registered: ‎11-11-2015

How to locate the original System Generator files in example design SSRIPDesign_1x1 (Vivado 2018.3)?

Hi everyone,

We purchased the ZCU111 board and I'm trying to understand an example design named "SSR IP Design (1x1)" for this board. This example design is a part of rdf0476-zcu111-RFdc-eval-tool-2018-3.zip package, which is downloadable from Xilinx website.

According to the steps described in Xilinx Wiki, the SSR IP design contains IP blocks that perform interpolation/decimation. If my understanding is correct, these IPs were generated by Xilinx System Generator. However, I'm unable to find original design files that can be opened by System Generator.

fir2_dec.png

As shown in the figure above, the fir2_dec_avinash IP should be generated by System Generator.

ip_repo.png

In the ip_repo folder, I can find folders named "decimation" and "interpolation", but they only contain the packaged IPs, and the System Generator design files are not contained.

Can anyone tell me where can I locate the original System Generator design files?

Thank you very much.

Regards,
Tong

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