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Visitor
Visitor
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Registered: ‎04-05-2020

I/O voltage levels of FMC pins in VC707

Hi,

I am trying to use the FMC pins on the VC707 board for I/O and powering my custom chip. My chip requires about 50+ I/O signals (3.3V) and two power pins (1.2V and 3.3V). I was thinking to use the VCC3V3 power pin and the adjustable VADJ as the two power pins. From the documentation and other posts, I understand that I will need to program the TI controller to adjust the VADJ to 1.2V.

However, my question is, how should I set the I/O pins to 3.3V signals. The datasheet and various other posts say that it is fixed at 1.8V logic (LVCMOS18 I/O standard as mentioned in the datasheet). Is there a way to make these I/O pins at 3.3V? Which rail in the FPGA needs to be set up to make these I/O pins to 3.3V?

Instead of 3.3V, I think my chip can also work with 2.5V. Any help is greatly appreciated!

Thanks!

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Xilinx Employee
Xilinx Employee
233 Views
Registered: ‎06-06-2018

Re: I/O voltage levels of FMC pins in VC707

Hi @agrawa64 ,

HP Banks can take max VCC of 1.8V, and HP Bank of FPGA are routed to FMC. Hence you cannot give more than 1.8V as VCC ( VADJ Voltage) to FMC Bank.

Hence VADJ Max value is 1.8V VCC.

Since VADJ is 1.8V (Max value), you cannot generate 3.3V/2.5V ( or greater than 1.8V) IO Signal from FMC Banks.

Regards,
Deepak D N
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