06-04-2011 10:45 PM
I have problems in implmenting the codes attached to XAPP1015 on the Saprtan3E FPGA Board CTXIL206.
The problem is that the timing constraint for the main clock (135MHz) could not be met and ISE claims that the constraint is "impossible to meet because component delays alone exceed the constraint". Actually the maximum achievable frequency is about 56 MHz which is far away from what has been expected.
Regarding to the page 68 of XAPP1015 which shows that the SD-SDI Codes have passed Static Timing Analysis and have been implemented on the board, could anyone guide me to solve this issue?
06-14-2011 11:05 PM
Thanks for your reply
I have solved the problem by changing (reducing) the clock of the modules which do not require high frequency clock, but the problem is that it has been claimed that these codes have been implemented on Spartan-3E.
I want to be sure that these codes are the same as the codes which has been claimed.
09-08-2011 12:11 AM
I think I've found a bug in the XAPP1015 verilog and VHDL code.
The line that has the comment "K28.1 special case" in the decoder_8b10.vhd/v file has the wrong constant. Instead of "100" or b100, it should be "001" or b001.