Dear Members;
I am tring to use MIG 7 (with axi) and create a mig project using ISE 14.6.
I like to create the example design and monitor the calibration complete and compare error signals to make sure that I was able to create a design correctly before moving to my custom board.
However I am having problems with the VC707 MIG design - the init_calibration_done never goes high and I receive phaselock_err = 1 error.
Instead of copying my settings here, I will write it down how I set up MIG step by step:
- I create a new project in ISE and choose the development board as VC707 and preferred language: Verilog (so that I can add AXI interface)
- After successfully creating the project, I add a new source from the IP core list -> MIG 7 series
Here are the page by page responses for the MIG tool
1) Create Design, 1 controller, with AXI interface
2) no pin compatible FPGAs
3) Select DDR3 SDRAM
4) Clock period: 2500ps (400 Mhz)
PHY to Controller Clock Ratio: 2:1
Components: SODIMMs
Part: MT8 JTF 128 64Hz - 1G6
Ordering: Normal
5) AXI datawidth: 128
Arbitration Scheme: WRITE_PRIORITY
Narrow Burst Support: 1
ID Width: 4
6) Input Clock period: 5000ps (200Mhz) -> My plan is to directly connect this to the 200 MHZ clock input on VC707
Read Burst Type: Sequential
Output Driver Impedance Control: RZQ/7
Controller Chip Select Pin: Disable
RTT - On Die Termination: RZQ/6
7) System Clock: Differential
Reference Clock: Use System Clock
Reset Polarity: Active Low
added debug signals for 1024
IO power reduction = ON
XADC Instantiation= ENABLED
Internal Vref = unchecked
8) DCI Cascade = checked
9) Preexisting Pinout know is fixed, I entered the pin locations from the user guide for VC707. Trying to read from the master ucf doesn't seem to work, I would like to know why.
10) sys_clk is in bank 38 E19/E18(P/N)
NO clk_ref
sys_rst -> no connect
init_calib_complete > no connect
tg_compare_error -> no connect
and click generate.
After the design is generated, I go to the folder -> example_design -> par and run create_ise.bat
which creates the test.xise. Then I start this project and run the place and route.
I perform the place and route successfully and generate the bitstream. However init_calib_complete never goes high.
When I look at the chipscope, I see that:
pi_phaselock_start and phase_locked_done are 1.
pi_dqsfound_start and pi_dqsfound_done are 1.
pi_dqsfound_fine_adjust_done is 1.
wrlvl_done is 1.
However
rdlvl_err is 2.
Any ideas what I might be doing wrong? Since I am using VC707, I was expecting this to be a little more straightforward.
I also added the ucf file in case it is needed.
Regards,
