02-27-2010 03:15 AM
Just a newbie question: The ML506 board comes with a 100 MHz single ended clock, and the onboard IDT5V9885 clock generator IC provides 200 MHz deifferential clock as well. Can I generate 1GHz clock from either of the two clocks? And secondly, if I do manage to design something for 1GHz operation, can the Virtex-5 actually operate at this speed? Thanks in advance.
02-27-2010 05:43 AM
Since the Virtex-5 series DCM maxes out at 450MHz-550MHz depending on speed grade and the PLL runs from 450MHz to 710MHz depending on device and speed grade, you cannot generate a 1 GHz clock with the ML506. You may, however, produce a 1Gb/s interface using DDR logic built into the FPGA circuitry.
The I/O are good up to 1.25Gb/s with the LVDS interface but only 800Mb/s on single-ended.
02-27-2010 09:31 AM
02-27-2010 09:49 AM
The issue is with the capabilities of the FPGA: it's clock distribution capabilities and the associated I/O. Take a look at the data sheet for the specific FPGA device on your board and you'll find in the DC and AC switching characteristics limit the performance. I haven't looked at the ML605 myself (I'm just another engineer who works with Xilinx devices more than with Xilinx boards) but imagine there's not yet 2Gb/s general I/O.
If you want to use the MGT transcievers, youhave to have a device/board with the MGTs and capable of 2Gb/s operation to deliver a 1Gb/s clock.
02-27-2010 10:18 PM