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Newbie
Newbie
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Registered: ‎07-08-2020

Is There A Documentation Error on VC707 FMC Mapping

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I am using Xilinx VC707 Eval Board. I have connected an output signal to FPGA Pin M31. From the ug885, page-64, Signal M31 should get muxed to FMC1 G3. I found the Signal on FMC2 G13. Has anyone seen this?

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240 Views
Registered: ‎01-22-2015

@RFatSTS 

For the VC707 board, I find all the following sources agree that FPGA pin-M31 is routed directly to pin-G3 of connector, FMC1:

  • Schematic
  • UG885
  • master constraints file, VC707_rev_2.0.ucf.xdc

So, I suspect the VC707 documentation is correct about this connection.

It is possible that your firmware/RTL has routed the same signal to both pins M31 and pin AE42 of the FPGA – which would send the signal to FMC1-G3 and FMC2-G13. 

Your RTL will reference the port names (FMC1_HPC_CLK1_M2C_N and FMC2_HPC_LA08_N) rather than the pin names (M31 and AE42).   So, look in your RTL and see what signals are connected to ports FMC1_HPC_CLK1_M2C_N and FMC2_HPC_LA08_N.

Cheers,
Mark

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241 Views
Registered: ‎01-22-2015

@RFatSTS 

For the VC707 board, I find all the following sources agree that FPGA pin-M31 is routed directly to pin-G3 of connector, FMC1:

  • Schematic
  • UG885
  • master constraints file, VC707_rev_2.0.ucf.xdc

So, I suspect the VC707 documentation is correct about this connection.

It is possible that your firmware/RTL has routed the same signal to both pins M31 and pin AE42 of the FPGA – which would send the signal to FMC1-G3 and FMC2-G13. 

Your RTL will reference the port names (FMC1_HPC_CLK1_M2C_N and FMC2_HPC_LA08_N) rather than the pin names (M31 and AE42).   So, look in your RTL and see what signals are connected to ports FMC1_HPC_CLK1_M2C_N and FMC2_HPC_LA08_N.

Cheers,
Mark

View solution in original post

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Moderator
Moderator
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Registered: ‎06-14-2010

Hello @RFatSTS ,

Is there any further assistance required in relation to this matter? If so, please let us know and we will be glad to help you further then.

However if your issue is resolved now, please mark a response as 'Accepted Solution' (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions), so that the topic can be completed then.

We appreciate your help.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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