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Observer wadenaka87
Observer
1,533 Views
Registered: ‎09-20-2017

Is XM105 compatible with the KCU116 eval board?

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Hi,

 

I'm attempting to use the XM105 FMC debug card with the KCU116 eval board but I only see DS6 (XM105 +12V input power good) illuminated.  Board Power Good and XM105 VADJ input power good LEDs are off.   Has anyone had success in using this debug card?

 

Thanks,

 

-Wade

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Observer wadenaka87
Observer
2,330 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

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I was able to follow the instructions for https://www.xilinx.com/support/answers/68521.html to setup the SCUI tool to allow me to set the VADJ.  Now I see all three LEDs illuminated.

 

Thanks,

 

-Wade

View solution in original post

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9 Replies
Xilinx Employee
Xilinx Employee
1,514 Views
Registered: ‎08-01-2008

Re: Is XM105 compatible with the KCU116 eval board?

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yes please refer this ARs
https://www.xilinx.com/support/answers/69859.html
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
1,499 Views
Registered: ‎08-01-2012

Re: Is XM105 compatible with the KCU116 eval board?

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VCU118 can be supported using modules compatible with the VITA-57.1 FPGA mezzanine card (FMC) and VITA-57.4 FPGA mezzanine card plus high serial pin (FMC+ HSPC) connectors on the VCU118 board. XM105 is VITA-57.1 compatible debug card. So according to that s XM105 compatible with the KCU116 eval board. 

 

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Moderator
Moderator
1,495 Views
Registered: ‎07-23-2015

Re: Is XM105 compatible with the KCU116 eval board?

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@wadenaka87 KCU116 which is an Ultrascale board implements the setting of VADJ voltage by reading the EEPROM content of FMC card. Since XM105 is an older board and doesn't have EEPROM data, KCU116 doesn't set the VADJ voltage. You can set it manually and use XM105. 

 

Check this AR for more details on how to set VADJ manually: https://www.xilinx.com/support/answers/62178.html

 

 

- Giri
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There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
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Observer wadenaka87
Observer
1,481 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

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@gnarahar I followed the instructions and saw the following at the output of my terminal:

Starting System Controller...
:P~
Detected an FMC...

Getting appropriate VADJ value...
:P~
Setting VADJ on address 18...
:P~
Running on boot command: 0

Running on boot command: 1

Running on boot command: 2

Running on boot command: 3

Running on boot command: 4

Running on boot command: 5

Running on boot command: 6

Running on boot command: 7

Running on boot command: 8
:P~80072021d8a0d
Running on boot command: 9

System Controller Initialization Finished...

 

The terminal does not seem to respond to any inputs after that, please advise.

 

Thanks,

 

-Wade

 

 

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Observer wadenaka87
Observer
2,331 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

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I was able to follow the instructions for https://www.xilinx.com/support/answers/68521.html to setup the SCUI tool to allow me to set the VADJ.  Now I see all three LEDs illuminated.

 

Thanks,

 

-Wade

View solution in original post

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Observer wadenaka87
Observer
1,459 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

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Unfortunately, after I programmed my bitfile onto the board the power good and XM105 VADJ input power good turned off.  When I connect a terminal to the USB UART the system controller hangs at:

 

Starting System Controller...
010

 

All operations performed though the SCUI tool timeout.  Is there a way to restore the firmware for the system controller?

 

Thanks,

 

-Wade

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Observer wadenaka87
Observer
1,446 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

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I've found that pressing SW5 to clear the FPGA program causes the VCC3V3_PGOOD (DS4) to come back on and the System Controller successfully initializes.  Is it possible that something in my constraints file is causing DS4 to turn off?  I'm thinking that may be preventing me from programming the VADJ value via the SCUI tool.

 

The following is from my constraints file:


# User Configuration
# Link Width   - x2
# Link Speed   - Gen2
# Family       - kintexuplus
# Part         - xcku5p
# Package      - ffvb676
# Speed grade  - -2
# Xilinx Reference Board is KCU116
###############################################################################
# User Time Names / User Time Groups / Time Specs
###############################################################################
##
## Free Running Clock is Required for IBERT/DRP operations.
##
# Clock for the 300 MHz clock is already created in the Clock Wizard IP.
# 300 MHz clock pin constraints.
set_property IOSTANDARD DIFF_SSTL12 [get_ports free_run_clock_p_in]
set_property IOSTANDARD DIFF_SSTL12 [get_ports free_run_clock_n_in]
set_property PACKAGE_PIN K22 [get_ports free_run_clock_p_in]
set_property PACKAGE_PIN K23 [get_ports free_run_clock_n_in]
#


# bitfile / bitstream options
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]

#############################################################################################################
create_clock -period 10.000 -name sys_clk [get_ports sys_clk_p]


#
#############################################################################################################
set_false_path -from [get_ports sys_rst_n]
set_property PULLUP true [get_ports sys_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]
set_property PACKAGE_PIN T19 [get_ports sys_rst_n]
set_property CONFIG_VOLTAGE 1.8 [current_design]
#set_property CFGBVS GND [current_design]
set_property CFGBVS VCCO [current_design]


set_property IOSTANDARD LVCMOS18 [get_ports led_0]
set_property IOSTANDARD LVCMOS18 [get_ports led_1]
set_property IOSTANDARD LVCMOS18 [get_ports led_2]
set_property IOSTANDARD LVCMOS18 [get_ports led_3]
set_property IOSTANDARD LVCMOS18 [get_ports led_4]
set_property IOSTANDARD LVCMOS18 [get_ports led_5]
# LEDs for KCU116
# sys_resetn
set_property PACKAGE_PIN C9 [get_ports led_0]
# axi resetn
set_property PACKAGE_PIN D9 [get_ports led_1]
# user_link_up

set_property PACKAGE_PIN E10 [get_ports led_2]
# cfg_current_speed[0] => 00: Gen1; 01: Gen2; 10:Gen3; 11:Gen4
# Clock Up/Heart Beat(HB)
set_property PACKAGE_PIN E11 [get_ports led_3]
set_property PACKAGE_PIN F9 [get_ports led_4]
set_property PACKAGE_PIN F10 [get_ports led_5]


#
set_property PACKAGE_PIN V6 [get_ports sys_clk_n]
set_property PACKAGE_PIN V7 [get_ports sys_clk_p]



#
# ASYNC CLOCK GROUPINGS
# sys_clk vs TXOUTCLK
# set_clock_groups -name async18 -asynchronous -group [get_clocks sys_clk] -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
# set_clock_groups -name async19 -asynchronous -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -group [get_clocks sys_clk]
set_clock_groups -name async18 -asynchronous -group [get_clocks sys_clk] -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_clock_groups -name async19 -asynchronous -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -group [get_clocks sys_clk]


#
# sys_clk vs intclk
set_clock_groups -name async25 -asynchronous -group [get_clocks -of_objects [get_pins xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O]] -group [get_clocks sys_clk]
set_clock_groups -name async26 -asynchronous -group [get_clocks sys_clk] -group [get_clocks -of_objects [get_pins xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/phy_clk_i/bufg_gt_intclk/O]]
#
# clk_300MHz vs TXOUTCLK
#set_clock_groups -name async22 -asynchronous -group [get_clocks -of_objects [get_ports free_run_clock_p_in]] -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
#set_clock_groups -name async23 -asynchronous -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -group [get_clocks -of_objects [get_ports free_run_clock_p_in]]

# TXOUTCLK vs sys_clk
set_clock_groups -name async30 -asynchronous -group [get_clocks sys_clk] -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]]
set_clock_groups -name async31 -asynchronous -group [get_clocks -of_objects [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -group [get_clocks sys_clk]

# TXOUTCLK versus 100MHz IP Clock
#set_clock_groups -name async67 -asynchronous -group [get_clocks {xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}] -group [get_clocks -of_objects [get_pins mem_clk_inst/inst/plle4_adv_inst/CLKOUT0]]
#set_clock_groups -name async68 -asynchronous -group [get_clocks -of_objects [get_pins mem_clk_inst/inst/plle4_adv_inst/CLKOUT0]] -group [get_clocks {xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]

set_clock_groups -name async67 -asynchronous -group [get_clocks {xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}] -group [get_clocks clk_out1_clk_wiz_0]
set_clock_groups -name async68 -asynchronous -group [get_clocks clk_out1_clk_wiz_0] -group [get_clocks {xdma_0_i/inst/pcie4_ip_i/inst/gt_top_i/diablo_gt.diablo_gt_phy_wrapper/gt_wizard.gtwizard_top_i/xdma_0_pcie4_ip_gt_i/inst/gen_gtwizard_gtye4_top.xdma_0_pcie4_ip_gt_gtwizard_gtye4_inst/gen_gtwizard_gtye4.gen_channel_container[1].gen_enabled_channel.gtye4_channel_wrapper_inst/channel_inst/gtye4_channel_gen.gen_gtye4_channel_inst[0].GTYE4_CHANNEL_PRIM_INST/TXOUTCLK}]

#
#
#
# The below PINs are asynchronous inputs to the GT block.
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/RXPRGDIVRESETDONE]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXPRGDIVRESETDONE]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/PCIESYNCTXSYNCDONE]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/GTPOWERGOOD]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/CPLLLOCK]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/PCIERATEGEN3]
#set_false_path -through [get_pins -hierarchical -filter NAME=~*gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/RXELECIDLE]
#
#
# These pins are dynamic and added case analysis constrains. so that tool do not complain any warnings.
#set_case_analysis 1 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXRATE[0]}]
#set_case_analysis 1 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/RXRATE[0]}]
#set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXRATE[1]}]
#set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/RXRATE[1]}]
#set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/TXRATE[2]}]
#set_case_analysis 0 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[*].*gen_gtye4_channel_inst[*].GTYE4_CHANNEL_PRIM_INST/RXRATE[2]}]
#
#


#
set_false_path -to [get_pins -hier {*sync_reg[0]/D}]
# set_false_path -to [get_pins -hier {*sync_reg[0]/D}]
#


#set_property PACKAGE_PIN D13       [get_ports TTCLK]
set_property IOSTANDARD LVCMOS18 [get_ports TTCLK]


# Prohibit the use of package pin N21,  This should prevent errors related to EMCCLK, which is not used in this design
set_property prohibit 1 [get_sites N21]

set_property IOSTANDARD LVCMOS18  [get_ports debug_awvalid]
set_property IOSTANDARD LVCMOS18  [get_ports debug_awready]
set_property IOSTANDARD LVCMOS18  [get_ports debug_wlast]
set_property IOSTANDARD LVCMOS18  [get_ports debug_wvalid]
set_property IOSTANDARD LVCMOS18  [get_ports debug_wready]
set_property IOSTANDARD LVCMOS18  [get_ports debug_bvalid]
set_property IOSTANDARD LVCMOS18  [get_ports debug_bready]
set_property IOSTANDARD LVCMOS18  [get_ports debug_axi_clk]
set_property IOSTANDARD LVCMOS18  [get_ports debug_clk]
set_property IOSTANDARD LVCMOS18  [get_ports debug_cs]
set_property IOSTANDARD LVCMOS18  [get_ports debug_wrack]

set_false_path -to  [get_ports debug_awvalid]
set_false_path -to  [get_ports debug_awready]
set_false_path -to  [get_ports debug_wlast]
set_false_path -to  [get_ports debug_wvalid]
set_false_path -to  [get_ports debug_wready]
set_false_path -to  [get_ports debug_bvalid]
set_false_path -to  [get_ports debug_bready]
set_false_path -to  [get_ports debug_axi_clk]
set_false_path -to  [get_ports debug_clk]
set_false_path -to  [get_ports debug_cs]
set_false_path -to  [get_ports debug_wrack]

# J1-25
set_property PACKAGE_PIN Y20 [get_ports debug_awvalid]
# J1-27
set_property PACKAGE_PIN Y21 [get_ports debug_awready]
# J1-2
set_property PACKAGE_PIN AF18 [get_ports debug_wlast]
# J1-4
set_property PACKAGE_PIN AF19  [get_ports debug_wvalid]
# J1-16
set_property PACKAGE_PIN AE22   [get_ports debug_wready]
# J1-20
set_property PACKAGE_PIN AF22   [get_ports debug_bvalid]
# J1-34
set_property PACKAGE_PIN AA22   [get_ports debug_bready]
# J1-36
set_property PACKAGE_PIN AB22  [get_ports debug_axi_clk]
# J1 - 5
set_property PACKAGE_PIN AC19  [get_ports debug_clk]
# J1 - 7
set_property PACKAGE_PIN AD19  [get_ports debug_cs]
# J1 - 21
set_property PACKAGE_PIN AA19  [get_ports debug_wrack]

set_property  PACKAGE_PIN    AB19              [get_ports "FMC_HPC0_LA05_N"]  
set_property  IOSTANDARD     LVCMOS18              [get_ports "FMC_HPC0_LA05_N"]


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Observer wadenaka87
Observer
1,436 Views
Registered: ‎09-20-2017

Re: Is XM105 compatible with the KCU116 eval board?

Jump to solution

I realized that the tool had assigned FPGA pins to ports that I had not explicitly assigned.  The I2C pins that control the power settings had been reassigned and that was causing my FMC board to not come up properly.

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Moderator
Moderator
1,397 Views
Registered: ‎07-23-2015

Re: Is XM105 compatible with the KCU116 eval board?

Jump to solution

@wadenaka87 Thanks for the updates. Seems like you were able to debug the issue and are good to go from your last post. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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