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Newbie
Newbie
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Registered: ‎06-28-2019

JESD Data Sample Mapping

I am trying to implement the JESD protocol on the kcu105 eval board using the JESDv7.2 core. I am using 8 lanes for data, and I achieve the right mapping to reconstruct the samples. The user guide doesn't have examples for 8 lanes. 

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Participant
Participant
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Registered: ‎10-07-2016

I have the same question, but will expand on the original quesion as follows: JESD Link info: (F=2, K=32, reference clock is 150mhz, 16 bit samples)


There are 16bit samples coming across JESD lanes 0-7 at a lane rate of 6Gbps. and a core clock of 150MHz, The core outputs 256bits, or sixteen 16-bit samples. 

Thus, there are 8 samples incoming across 8 lanes as input and the output of the core is 16 samples outgoing

Question: What is the order of the 16 bit samples across the 256 bit bus: m_axi_rx[255:0]? 

E.g., I know from testing that it is *not* the following, but what is it?  

  • m_axi_rx[15:   0] = 1st sample(15:0) received from lane 0 ?
  • m_axi_rx[31:  16] = 1st sample(15:0) received from lane 1 ?
  • m_axi_rx[47:  32] = 1st sample ... from lane 2 ?
  • m_axi_rx[63:  48] = 1st sample from lane 3 ?
  • m_axi_rx[79:  64] = 1st sample from lane 4 ?
  • m_axi_rx[95:  80] = 1st sample from lane 5 ?
  • m_axi_rx[111: 96] = 1st sample from lane 6 ?
  • m_axi_rx[127:112] = 1st sample from lane 7 ?
  • m_axi_rx[143:128] = 2nd sample from lane 0 ?
  • m_axi_rx[159:144] = 2nd sample from lane 1 ?
  • m_axi_rx[175:160] = 2nd sample from lane 2 ?
  • m_axi_rx[191:176] = 2nd sample from lane 3 ?
  • ...
  • m_axi_rx[255:240] = 2nd sample from lane 7 ?

 

What is the actual sample and bit order? 

Thank you.

 

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Registered: ‎09-10-2018

Hi,

 

Have a look at the transport layer example in the JESD example project. If you have 8 lanes, you will need 256 wide bus (unfortunately i coundt fing a way to make a bus (in the JESD core wider to send more samples))

This is how I map my samples:

lane0_data_reg <= dac0_sample0(15 downto 8) & dac0_sample1(15 downto 8) & dac0_sample2(15 downto 8) & dac0_sample3(15 downto 8);
lane1_data_reg <= dac0_sample0(7 downto 0) & dac0_sample1(7 downto 0) & dac0_sample2(7 downto 0) & dac0_sample3(7 downto 0) ;
lane2_data_reg <= dac1_sample0(15 downto 8) & dac1_sample1(15 downto 8) & dac1_sample2(15 downto 8) & dac1_sample3(15 downto 8);
lane3_data_reg <= dac1_sample0(7 downto 0) & dac1_sample1(7 downto 0) & dac1_sample2(7 downto 0) & dac1_sample3(7 downto 0) ;
lane4_data_reg <= dac2_sample0(15 downto 8) & dac2_sample1(15 downto 8) & dac2_sample2(15 downto 8) & dac2_sample3(15 downto 8);
lane5_data_reg <= dac2_sample0(7 downto 0) & dac2_sample1(7 downto 0) & dac2_sample2(7 downto 0) & dac2_sample3(7 downto 0) ;
lane6_data_reg <= dac3_sample0(15 downto 8) & dac3_sample1(15 downto 8) & dac3_sample2(15 downto 8) & dac3_sample3(15 downto 8);
lane7_data_reg <= dac3_sample0(7 downto 0) & dac3_sample1(7 downto 0) & dac3_sample2(7 downto 0) & dac3_sample3(7 downto 0) ;

Here I send 4 samples per DAC channel. If you want to send 8 samples try dividing the jesd_core_clk by 2 and mux them (this is what i am trying to do rn. I am writing this while I am waiting for vivado to build the bitstream :))

NOTE: you transport layer will depend on the ADC / DAC that you are using.

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Moderator
Moderator
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Registered: ‎10-19-2011

• JESD204 in 8b10b is an 8 bit protocol.
• An ADC takes N bit samples (16bit in this case) and maps these into bytes. The ADC data sheet will tell you how this is done (in this case it could be [15:8] followed by [7:0] or [7:0] followed by [15:8]) I would guess the latter.
• For each lane our RX receives bytes 0 then 1 then 2 then 3. It then concatenates these bytes into a 32bit word as {3,2,1,0} (ie byte 3 becomes [31:24] ……… byte 0 becomes [7:0])
• The outshout of the core all the lanes concatenated together (ie LN[31:0,…… L1[31:0], L0[31:0], where L1[31:0] is rx_tdata[63:32] and L0[31:0] is rx_tdata[31:0]. Etc…)
• How you get your sample from this depends on how the ADC put the samples in!


If we assume that the convertor maps as [7:0] followed by [15:8] then the output would be…

First JESD data transmitted on Lane 0: jesd_rx[15:0] lane 0 sample data = 0x0
First JESD data transmitted on Lane 1: jesd_rx[15:0] lane 1 sample data = 0x1
First JESD data transmitted on Lane 2: jesd_rx[15:0] lane 2 sample data = 0x2
First JESD data transmitted on Lane 3: jesd_rx[15:0] lane 3 sample data = 0x3
First JESD data transmitted on Lane 4: jesd_rx[15:0] lane 4 sample data = 0x4
First JESD data transmitted on Lane 5: jesd_rx[15:0] lane 5 sample data = 0x5
First JESD data transmitted on Lane 6: jesd_rx[15:0] lane 6 sample data = 0x6
First JESD data transmitted on Lane 7: jesd_rx[15:0] lane 7 sample data = 0x7

Second transfer of JESD data transmitted on Lane 0: jesd_rx[15:0] lane 0 sample data = 0x8
Second transfer of JESD data transmitted on Lane 1: jesd_rx[15:0] lane 1 sample data = 0x9
Second transfer of JESD data transmitted on Lane 2: jesd_rx[15:0] lane 2 sample data = 0xa
Second transfer of JESD data transmitted on Lane 3: jesd_rx[15:0] lane 3 sample data = 0xb
Second transfer of JESD data transmitted on Lane 4: jesd_rx[15:0] lane 4 sample data = 0xc
Second transfer of JESD data transmitted on Lane 5: jesd_rx[15:0] lane 5 sample data = 0xd
Second transfer of JESD data transmitted on Lane 6: jesd_rx[15:0] lane 6 sample data = 0xe
Second transfer of JESD data transmitted on Lane 7: jesd_rx[15:0] lane 7 sample data = 0xf


With the input defined, what will appear on the core output?


• m_axi_rx[15: 0] =0x0
• m_axi_rx[31: 16] =0x8
• m_axi_rx[47: 32] =0x1
• m_axi_rx[63: 48] =0x9
• m_axi_rx[79: 64] =0x2
• m_axi_rx[95: 80] =0xa
• m_axi_rx[111: 96] =0x3
• m_axi_rx[127:112] =0xb
• m_axi_rx[143:128] =0x4
• m_axi_rx[159:144] =0xc
• m_axi_rx[175:160] =0x5
• m_axi_rx[191:176] =0xd
• ...
• m_axi_rx[255:240] = 0xf

If the converter maps [15:8] followed by [7:0] then you will have to swap the bytes in each of these 16 bits.

I hope this gets you on the right track!
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