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Adventurer
Adventurer
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Registered: ‎10-13-2016

JESD204B reference design for TI DAC and KC705

Hi,

We are having the DAC EVM DAC38J84 and KC705 evaluation board.
we want to implement the reference design slac690c which implements the  JESD204B interface

To work with this reference design we need the TSW14J10 FMC-USB Interposer Card to communicate
with the HSDC pro software.

at present we have only the DAC38J84 EVM and KC705 EVM( XILINX FPGA).
we need to remove the functionality of TWS14J10 from the reference design.

 


we have gone through the JESD204_TI_reference_design.pdf file

In above pdf it is mentioned that the SPI2 is used as a control interface for the FPGA.

using this control interface the HSDC pro software is writing into the writable bank addressing (page 15 of
JESD204_TI_reference_design.pdf).

There are three register banks BANK0, BANK1 and BANK2

BANK0 = for controlling sub-system

BANK1 = configure JESD204b receiver ip registers.

Bank2 = configure JESD204b transmitter ip registers.


We are not able to find these BANKs in the block diagram design of reference design.

We need a procedure to directly access these register BANKs and write the corresponding register value in
the reference design.

Thanks and Regards

Gaonkar

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