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Observer vnhegde
Registered: ‎08-29-2018

JTAG configuration for emulated DSP on Zedboard



We are facing an issue of JTAG clock is not getting driven by debugger in setup detailed below. I wanted to check, if  we need to use the 20pin-to-14pin JTAG adapter board in below scenario to overcome the issue. 

I am using Flyswatter2 debugger with 20-pin JTAG connector for debugging emulated DSP on FPGA of Zedboard (zynq 7000). Note that we are routing JTAG signals from emulated Tensilica core to 12-pin PMOD connector(JA1)  on Xilinx Zedboard. And the routed signals are hardwired to 20-Pin JTAG connector readily available with Flyswatter2 debugger. The connection diagram is attached herewith.  We are not using the standard 14-pin JTAG interface on our board. And we are using PMOD for JTAG interface as part of standalone bring-up of Tensilica core on FPGA.


Some signals on the 20-pin connector are floating. Also all signals driven from that 20-in connector need to be pulled high on our FPGA board..and we don't see these pull up resistors on our board. We have added pull-up resistor using xdc constraint in our design but not sure if it is sufficient.


Please let us know your suggestions on this.




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Registered: ‎08-10-2007

Re: JTAG configuration for emulated DSP on Zedboard

Zedboard is not a Xilinx Evaluation Kit, so it might be worth following up with http://zedboard.org/ for further support in relation to this.

Don’t forget to reply, kudo, and accept as solution.
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