why Platform Cable USB II and Xilinx Parallel Cable IV assignment pins differents than 14 pin Jtag standard pin assignment (like showed in http://hri.sourceforge.net/tools/jtag_faq_org.html#_Toc63218715 ) , are they realy different ? if yes is there custom adapter converts this 14 pin to the standard 20 pin ?
JTAG is an IEEE standard that defines a low level basic protocol with 4 mandatory
pins (TDI, TDO, TMS, TCK) and 1 optional pin (TRST). The connector style/pinout/etc (if
there even is one) is irrelevant so long as the protocol is followed.
How someone communicates to the physical JTAG chain is not defined so there are many different implementations and software drivers/APIs for each physical implementation.
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