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kashifwajid
Visitor
Visitor
5,414 Views
Registered: ‎06-13-2016

KC705 Partial Reconfiguration Timing Calculations Using PR Controller

Hello,

 

I am trying to follow the tutorial from Xilinx for Partial Reconfiguration controller using KC705 Board. I have followed all the steps given in there and loaded the Micron flash - 28f00ap30t with the required bitstreams. The flash was programmed using the write_cfgmem command. I use the hardware triggers given on the board (push buttons) to load the desire partial bitstream. Now I want to calculate how many clock cycles it takes for the FPGA to be reconfigured when a hardware trigger is sent. 

 

The following code counts the number of clock cycles:

if clk'event and clk = '1'then
        --rm_status_in is the status of the PR Controller 
	if rm_status_in(2 downto 0) = "100" and start_counting = '0' then
		start_counting <= '1';
		count <= 0;
	elsif rm_status_in(2 downto 0) = "111" then
		start_counting <= '0';
	end if;
	
	if start_counting = '1' then
		count <= count + 1;
	end if;
	
	time_count_out <= count; -- output the counts
end if;

The status has been taken from PG193 partial reconfiguration controller page 25.

For example, I selected a partial block containing SLICE_X0Y100:SLICE_X5Y149. It generates a partial bit-stream of 320 KB. 
When I send a hardware signal to reconfigure this partial block with a new design it takes 1806113 clock cycles to reconfigure. This comes out to be 18 ms using a 100 Mhz clock 

While according to the ICAP documentation using a 100Mhz clock and ICAP width set to 32-bit is should reconfigure that block in 0.82 ms.

Please, can anyone help me in finding that how can I accurately measure the time (or clock cycles) it takes to configure a partial block using ICAP and PR Controller.

Thank you.

 

Kashif Wajid 

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1 Reply
drobins
Xilinx Employee
Xilinx Employee
4,605 Views
Registered: ‎10-04-2011

Hi Kashif,

  your code to calculate the PR time looks ok to me.  The 18ms load time doesn't surprise me - you're loading bitstreams from flash memory which can be very slow.  If you put an ILA on the PRC's memory interface you'll be able to monitor the number of wait-states between the PRC requesting data and the data actually arriving. 

 

You'll get the fastest load times if you preload the bitstreams into DDR memory and then fetch them from there.   Examples 1 & 2 in app note XAPP1292 use TFTP to fetch bitstreams into DDR and then load them using the PRC. They are for the KC705 board so you might be able to use them directly, or at least get some ideas from them.

 

Cheers

David

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