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Registered: ‎12-29-2019

KC705 and Vivado 2019.2

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I've bought the KC705 and have downloaded Vivado 2019.2, but I cannot get any of the reference designs to build. I'm also trying to do a really simply Verilog program that blinks the LEDs, but the the compiler complains about constraints, and no matter what I put in them, it won't build. I found an old master xdc file for KC705, but it won't build either. 

So, how are you supposed to do designs with the KC705? Should you download 2014.x version instead, or is there an up-to-date xdc that actually compiles on 2019.2?

 

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Registered: ‎06-14-2010

Hello leif@rdos.net ,

This topic is still open and is waiting for you.

If your issue is not solved yet, please reply in the thread, so that we can assist you with your issue.

However, if your question is answered and/or your issue is solved, please mark a response as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. We appreciate your help.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Registered: ‎09-15-2016

Hi leif@rdos.net 

Can you show what is the exact error you get? Design on KC705 should build successfully on 2019.2 with proper contraints used.

Regards
Rohit
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Moderator
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Registered: ‎06-14-2010

Hello leif@rdos.net ,

This topic is still open and is waiting for you.

If your issue is not solved yet, please reply in the thread, so that we can assist you with your issue.

However, if your question is answered and/or your issue is solved, please mark a response as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. We appreciate your help.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Don’t forget to reply, kudo, and accept as solution.
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Registered: ‎12-29-2019

I suppose most of it is not relevant anymore. There are problems with the documentation, and constraint files, but it's possible to solve. At least the PCIe project does build without much fuss with 2019.2, but the SDRAM won't (because of contraints). You really should update the documents and source files so they build with the latest Vivado version. Many newcomers might use KC705, and if they cannot build reference projects, they might just give up and move on to something else.

 

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