03-07-2018 04:05 PM
I have consulted the KCU105 User Guide [UG917 (v1.8) July 26, 2017], Appendix D "Master Constraints File Listing". I have also generated a DDR4 core (using Vivado 2016.4) and its example design, including a constraints file example_design.xdc. Unfortunately the information in these two sources seems contradictory. To give just two examples,
In ug917 DQ is AE23 (AE23 is ADR in the example design).
In the example design DQ is AM22 (AM22 is DQ in ug917).
The 300MHz clock (sys_clk_p or SYSCLK_300_P)
In ug917 SYSCLK_300_P is AK17 (AK17 is DQ in the example design)
In the example design sys_clk_p is AJ23 (AJ23 is DQ in ug917).
These two sources are both specifically about the KCU105 board (not the generic defaults). Which should I believe?
03-08-2018 02:27 AM
I did do that (the example design's Vivado even displayed a picture of the board); but the pin arrangements are different. But thanks for the message.
03-27-2018 05:12 AM
Sorry for the delay in replying. Yes, the last suggestion made the problem disappear -- literally. All the explicit pin locations vanished from the constraints file, and were replaced, for each pin, by a constraint saying in effect that they should go wherever the board said they should go.
The example design still didn't synthesize for me though. Vivado said that two pins (the calibration-complete pin from the core and the pass/fail pin from the testbench) didn't have their IOSTANDARD specified, and I couldn't find a way to get past that successfully. So I'm afraid I gave up, and went to my own design instead, which I got successfully working (though I have another question about it, which I'll ask on a separate thread),
Thanks for the help.