KCU105 System Controller accesses i2c bus *after* configuring the FPGA
I have a design that implements an i2c controller which controls the SI570 clock. During initialization my design configures the i2c multiplexer. Everything works fine when I configure the FPGA with vivado over JTAG.
However, when I wrote the bit file to an SD card and used the system controller to boot the FPGA I found that my design no longer worked. Investigation revealed that the i2c mux had somehow been reset. I then found that apparently the system controller manipulates the i2c bus after it configures the FPGA.
I confirmed this by using a bare design (i.e., without i2c controller in the logic) that uses a counter (initialized to zero in the bit file) running on the 300MHz system clock. The SCL line is monitored and the counter value latched when SCL is low.
I found that SCL is active until up to ~30ms after the design starts running when configuring the FPGA with the system controller (it is not active when booting from SPI or JTAG/vivado). Thus, if your design uses i2c devices and you intend to boot it off the SD card then you should delay i2c operation for > 30ms after boot-up.
I thought this information about undocumented (and surprising) behavior might be useful for others...